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TNETV6446AINZWT 数据表(PDF) 29 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 29 Page - Texas Instruments |
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29 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 2-8. RESET and JTAG Terminal Functions (continued) SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. – TDO B5 O/Z JTAG test-port data output DVDD18 IPU TDI A5 I JTAG test-port data input DVDD18 IPU TCK A6 I JTAG test-port clock input DVDD18 – RTCK B6 O/Z JTAG test-port return clock output DVDD18 JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 IPD TRST D7 I JTAG compatibility statement portion of this data manual (Section 6.25, IEEE DVDD18 1149.1 JTAG). IPU EMU1 C6 I/O/Z Emulation pin 1 DVDD18 IPU EMU0 D6 I/O/Z Emulation pin 0 DVDD18 Table 2-9. EMIFA Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. EMIFA BOOT CONFIGURATION This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is COUT2/ sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit-wide EMIFA IPD B5/ A17 I/O/Z data bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus, EM_WIDTH = 1. DVDD18 EM_WIDTH After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5 B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is COUT3/ sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when IPD B6/ B17 I/O/Z DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1. DVDD18 DSP_BT After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output B6. YOUT0/ IPD G5/ D15 I/O/Z DVDD18 AEAW0 YOUT1/ IPD G6/ D16 I/O/Z DVDD18 AEAW1 These pins are multiplexed between EMIFA and the VPBE. At reset, the input states YOUT2/ of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2, IPD G7/ D17 I/O/Z Peripheral Selection at Device Reset, for details. DVDD18 AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. YOUT3/ IPD R3/ D18 I/O/Z DVDD18 AEAW3 YOUT4/ IPD R4/ E15 I/O/Z DVDD18 AEAW4 EMIFA FUNCTIONAL PINS: ASYNC / NOR This pin is multiplexed between EMIFA and HPI. EM_CS2/ For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous C2 I/O/Z DVDD18 HCS memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous EM_CS3 B1 I/O/Z DVDD18 memories (i.e., NOR flash) or NAND flash. (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) (3) Specifies the operating I/O supply voltage for each signal Copyright © 2005–2010, Texas Instruments Incorporated Device Overview 29 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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