TNETV6446AINZWT datasheet(63/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

3.3

Bootmode

The device is booted through multiple means: pin states captured at reset, primary bootloaders within

internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot

modes, pin configurations, and register configurations required for booting the device, are described in the

following sections.

3.3.1

Bootmode Registers

The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status

of various pins required for proper boot are stored within these registers.

3.3.1.1

BOOTCFG Register Description

The BOOTCFG register (located at address 0x01C4 0014) contains the status values of the BTSEL1,

BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pins captured at the rising edge of RESET. The register

format is shown in Figure 3-3 and bit field descriptions are shown in Table 3-4. The captured bits are

software readable after reset.

Figure 3-3. BOOTCFG Register

RESERVED

DSP_BT

BTSEL

EM_WIDTH

DAEAW

R-0000 0000 0000 0000 0000 000

R-L

R-LL

R-L

R-LLLLL

LEGEND: R = Read; W = Write; L = pin state latched at reset rising; -n = value after reset

Table 3-4. BOOTCFG Register Description

NAME

DESCRIPTION

BTSEL

ARM Boot mode selection pin states (BTSEL1, BTSEL0) captured at the rising edge of RESET.

‘00’ indicates ARM boots from ROM (NAND Flash/SPI Flash).

‘01’ indicates that ARM boots from EMIFA (NOR Flash).

‘10’ indicates that ARM boots from ROM (HPI).

‘11’ indicates that ARM boots from ROM (UART0).

DSP_BT

DSP Boot mode selection pin state captured at the rising edge of RESET.

‘0’ sets ARM boot of C64x+.

‘1’ sets C64x+ self boot.

EM_WIDTH

EMIFA data bus width selection pin state captured at the rising edge of RESET.

‘0’ sets EMIFA to 8 bit data bus width

‘1’ sets EMIFA to 16 bit data bus width.

DAEAW

EMIFA address bus width selection pin states (AEAW[4:0]) captured at the rising edge of RESET. This configures

EMIFA address pins multiplexed with GPIO. See the GPIO and EMIFA Multiplexing tables (Table 3-9,Table 3-10,

and Table 3-11).

Device Configurations

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