ST7LITE49K2 datasheet(52/245 Pages) STMICROELECTRONICS

52 / 245 page

Supply, reset and clock management

ST7LITE49K2

52/245

Bit 0 = AVDIE Voltage detector interrupt enable bit

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag is set. The pending interrupt information is automatically cleared when

software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

7.5.4

AVD threshold selection register (AVDTHCR)

Reset value: 0000 0011 (003h)

Bits 7:5 = CK[2:0] internal RC prescaler selection

These bits are set by software and cleared by hardware after a reset. These bits select

the prescaler of the internal RC oscillator. See Figure 13: Clock management block

diagram on page 41 and Table 11.

If the internal RC is used with a supply operating range below 3.3 V, a division ratio of

at least 2 must be enabled in the RC prescaler.

Bits 4:2 = Reserved, must be cleared.

Bits 1:0 = AVD[1:0] AVD Threshold selection. These bits are used to select the AVD

threshold. They are set and cleared by software. They are set by hardware after a reset.

CK2

CK1

CK0

AVD1

AVD0

Read/write

Table 11.

Internal RC prescaler selection bits

CK2

CK1

CK0

fOSC

fRC/2

fRC/4

fRC/8

fRC/16

others

fRC

Table 12.

AVD threshold selection bits

AVD1

AVD0

Functionality

Low

Medium

High

AVD off

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