ST7LITE49K2 datasheet(91/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and

DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is

generated if the CMPIE bit is set.

In Single Timer mode the output compare function is performed only on CNTR1. The

difference between both the modes is that, in Single Timer mode, CNTR1 can be compared

with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0

or DCR1 and CNTR2 is compared with DCR2 or DCR3.

Note:

The output compare function is only available for DCRx values other than 0 (reset value).

Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers

and these values are transferred in Active Duty Cycle registers after an overflow event if the

corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these

active DCRx values with the counters.

Figure 44.

Block diagram of output compare mode (single timer)

Input capture mode

The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter

CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture

occurs, the ICF bit is set and the ATICR register contains the value of the free running

upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading

the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and

always contains the free running upcounter value which corresponds to the most recent

Input Capture. Any further Input Capture is inhibited while the ICF bit is set.

DCRx

OUTPUT COMPARE CIRCUIT

COUNTER 1

(ATCSR)

CMPIE

PRELOAD DUTY CYCLE REG0/1/2/3

ACTIVE DUTY CYCLE REGx

CNTR1

TRAN1

(ATCSR2)

OVF

(ATCSR)

CMPFx (PWMxCSR)

CMP

REQUEST

INTERRUPT

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