ST7LITE49K2 datasheet(60/245 Pages) STMICROELECTRONICS

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Interrupts

ST7LITE49K2

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The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and

I0 bits of the CC register are both set.

Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is

kept (Example: previous = CFh, write = 64h, result = 44h).

Caution:

If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previous one, the interrupt x is re-entered.

Otherwise, the software priority stays unchanged up to the next interrupt request (after the

IRET of the interrupt x).

Table 16.

Interrupt vector vs ISPRx bits

Vector address

ISPRx bits

FFFBh-FFFAh

I1_0 and I0_0 bits(1)

Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process

management.

FFF9h-FFF8h

I1_1 and I0_1 bits

...

FFE1h-FFE0h

I1_13 and I0_13 bits

Table 17.

Dedicated interrupt instruction set(1)

During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the

current software priority up to the next IRET instruction or one of the previously mentioned instructions.

Instruction

New description

Function/Example

HALT

Entering Halt mode

IRET

Interrupt routine return

Pop CC, A, X, PC

JRM

Jump if I1:0 = 11 (level 3)

I1:0 = 11

JRNM

Jump if I1:0 <> 11

I1:0 <> 11

POP CC

Pop CC from the Stack

Mem => CC

RIM

Enable interrupt (level 0 set)

Load 10 in I1:0 of CC

SIM

Disable interrupt (level 3 set)

Load 11 in I1:0 of CC

TRAP

Software trap

Software NMI

WFI

Wait for interrupt

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