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ST7LITE49K2 数据表(PDF) 53 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 245 page  ST7LITE49K2 Supply, reset and clock management 53/245 7.5.5 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h) Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware. 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware. 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared. Bit 0 = RC/AWU RC/AWU selection bit 0: RC enabled 1: AWU enabled (default value) 7 0 0000 AWU_FLAG RC_FLAG 0 RC/AWU Read/write Table 13. Clock register mapping and reset values Address (Hex.) Register label 76 5 4 3 2 1 0 003Ah MCCSR Reset Value - 0 - 0 - 0 - 0 - 0 - 0 MCO 0 SMS 0 003Bh RCCR Reset Value CR9 1 CR8 1 CR7 1 CR6 1 CR5 1 CR4 1 CR3 1 CR2 1 003Ch SICSR Reset Value - 0 CR1 1 CR0 1 WDGRF 0 - 0 LVDRF x AVDF x AVDIE x 003Dh AVDTHCR Reset Value CK2 0 CK1 0 CK0 0 - 0 - 0 - 0 AVD1 1 AVD0 1 0051h CKCNTCS R Reset Value - 0 - 0 - 0 - 0 AWU_ FLAG 1 RC_FLA G 0 - 0 RC/AWU 1 |
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