ST7LITE49K2 datasheet(51/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

Supply, reset and clock management

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7.5.3

System integrity (SI) control/status register (SICSR)

Reset value: 011x 0x00 (xxh)

Bit 7 = Reserved, must be kept cleared

Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately

after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer

to Section 7.1.1: Internal RC oscillator on page 38.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last reset was generated by the watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to

ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the

LVDRF flags areis used to select the reset source (see Table 10: Reset source selection on

page 51).

Bit 3 = Reserved, must be kept cleared

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled

by option byte, the LVDRF bit value is undefined.

The LVDRF flag is not cleared when another RESET type occurs (external or

watchdog), the LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can

not.

Bit 1 = AVDF Voltage detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit is set. Refer to Figure 19 and to Section for

additional details.

0: VDD over AVD threshold

1: VDD under AVD threshold

CR1

CR0

WDGRF

LVDRF

AVDF

AVDIE

Read/write

Table 10.

Reset source selection

RESET source

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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