ST7LITE49K2 datasheet(49/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

Supply, reset and clock management

49/245

Note:

Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD

levels are not correlated. Refer to Section 13.3.2 on page 195 and Section 13.3.3 on page

196 for more details.

Figure 19.

Using the AVD to monitor VDD

7.4.3

Low power modes

Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit

RESET

IF AVDIE bit = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT Cleared by

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

hardware

INTERRUPT Cleared by

reset

Table 8.

Low power modes

Mode

Description

Wait

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

Halt

The SICSR register is frozen.

The AVD remains active but the AVD interrupt cannot be used to exit from Halt

mode.

Table 9.

Description of interrupt events

Interrupt event

Event flag

Enable

Control

bit

Exit from

Wait

Exit from

Halt

AVD event

AVDF

AVDIE

Yes

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