ST7LITE49K2 datasheet(31/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

Data EEPROM

31/245

Figure 8.

Data EEPROM write operation

If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not

guaranteed.

5.4

Power saving modes

5.4.1

Wait mode

The DATA EEPROM can enter Wait mode on execution of the WFI instruction of the

microcontroller or when the microcontroller enters Active-Halt mode.The data EEPROM will

immediately enter this mode if there is no programming in progress, otherwise the data

EEPROM will finish the cycle and then enter Wait mode.

5.4.2

Active-halt mode

Refer to Wait mode.

5.4.3

Halt mode

The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt

instruction. Therefore the EEPROM will stop the function in progress, and data may be

corrupted.

5.5

Access error handling

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by a RESET action), the integrity of the data in

memory will not be guaranteed.

Byte 1

Byte 2

Byte 32

PHASE 1

Programming cycle

Read operation impossible

PHASE 2

Read operation possible

E2LAT bit

E2PGM bit

Writing data latches

Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

⇓ Row / byte ⇒

0123

...

Physical Address

00h...1Fh

20h...3Fh

...

Nx20h...Nx20h+1Fh

ROW

DEFINITION

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