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ST7LITE49K2 数据表(PDF) 65 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 65 Page - STMicroelectronics |
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65 / 245 page  ST7LITE49K2 Power saving modes 65/245 Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 9.4 Active-halt and Halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active- Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS IBIT ON ON 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF 0 ON CPU OSCILLATOR PERIPHERALS IBIT ON ON X 1) ON 256 CPU CLOCK CYCLE DELAY Table 20. Enabling/disabling Active-halt and Halt modes LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit ATCSRCK0 bit Meaning 0x x0 Active-halt mode disabled 00 x x 0111 1x x x Active-halt mode enabled x 101 |
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