ST7LITE49K2 datasheet(100/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

100/245

Bits 11:0 = CNTR1[11:0] Counter value

This 12-bit register is read by software and cleared by hardware after a reset. The

counter CNTR1 increments continuously as soon as a counter clock is selected. To

obtain the 12-bit value, software should read the counter value in two consecutive read

operations. As there is no latch, it is recommended to read LSB first. In this case,

CNTR1H can be incremented between the two read operations and to have an

accurate result when ftimer=fCPU, special care must be taken when CNTR1L values

close to FFh are read.

When a counter overflow occurs, the counter restarts from the value specified in the

ATR1 register.

Autoreload register (ATR1H)

Reset value: 0000 0000 (00h)

Autoreload register (ATR1L)

Reset value: 0000 0000 (00h)

Bits 11:0 = ATR1[11:0] Autoreload register 1:

This is a 12-bit register which is written by software. The ATR1 register value is

automatically loaded into the upcounter CNTR1 when an overflow occurs. The register

value is used to set the PWM frequency.

PWM output control register (PWMCR)

Reset value: 0000 0000 (00h)

Bits 7:0 = OE[3:0] PWMx output enable bits

These bits are set and cleared by software and cleared by hardware after a reset.

0: PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for

general purpose I/O)

1: PWM mode enabled

0000

ATR11

ATR10

ATR9

ATR8

Read/write

ATR7

ATR6

ATR5

ATR4

ATR3

ATR2

ATR1

ATR0

Read/write

0OE3

0OE2

0OE1

0OE0

Read/write

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