ST7LITE49K2 datasheet(104/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

104/245

Input capture register high (ATICRH)

Reset value: 0000 0000 (00h)

Bits 15:12 = Reserved.

Input capture register low (ATICRL)

Reset value: 0000 0000 (00h)

Bits 11:0 = ICR[11:0] Input Capture Data.

This is a 12-bit register which is readable by software and cleared by hardware after a

reset. The ATICR register contains captured the value of the 12-bit CNTR1 register

when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS).

Capture will only be performed when the ICF flag is cleared.

Break enable register (BREAKEN)

Reset value: 0000 0011 (03h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = BREN2 Break enable for counter 2 bit

This bit is read/write by software. It enables the break functionality for Counter2 if BA bit

is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set.

0: No Break applied for CNTR2

1: Break applied for CNTR2

Bit 0 = BREN1 Break enable for counter 1 bit

This bit is read/write by software. It enables the break functionality for Counter1. If BA

bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is

reset.

0: No Break applied for CNTR1

1: Break applied for CNTR1

0000

ICR11

ICR10

ICR9

ICR8

Read only

ICR7

ICR6

ICR5

ICR4

ICR3

ICR2

ICR1

ICR0

Read only

000

BREN2

BREN1

Read/write

ST7LITE49K2 数据表(PDF) 104 Page - STMicroelectronics

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