ST7LITE49K2 datasheet(103/245 Pages) STMICROELECTRONICS

103 / 245 page

ST7LITE49K2

On-chip peripherals

103/245

Bit 4 = BP2EN Break 2 pin enable bit

This bit is read/write by software and cleared by hardware after Reset.

0: BREAK2 pin disabled

1: BREAK2 pin enabled

Bits 3:2 = Reserved, must be kept cleared

Bit 1 = SWBR2 Switch Break for counter 2 bit

This bit is read/write by software. While BREN2 is set, it selects BA1 or BA2 to control

PWM2/3 if ENCNTR2 bit is set.

0: BA1 selected

1: BA2 selected

Bit 0 = SWBR1 Switch Break for counter 1 bit

This bit is read/write by software. While BREN1 is set, it selects BA1 or BA2 to control

PWM0/1 by default and also PWM2/3 if ENCNTR2 bit is reset.

0: BA1 selected

1: BA2 selected

PWMx duty cycle register High (DCRxH)

Reset value: 0000 0000 (00h)

Bits 15:12 = Reserved.

PWMx duty cycle register Low (DCRxL)

Reset value: 0000 0000 (00h)

Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value: this 12-bit value is written by software. It

defines the duty cycle of the corresponding PWM output signal (see Figure 40).

In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of

the PWMx output signal (see Figure 40). In Output Compare mode, they define the value to

be compared with the 12-bit upcounter value.

0000

DCR11

DCR10

DCR9

DCR8

Read/write

DCR7

DCR6

DCR5

DCR4

DCR3

DCR2

DCR1

DCR0

Read/write

ST7LITE49K2 数据表(PDF) 103 Page - STMicroelectronics

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