ST7LITE49K2 datasheet(47/245 Pages) STMICROELECTRONICS

47 / 245 page

ST7LITE49K2

Supply, reset and clock management

47/245

7.4

System integrity management (SI)

The System Integrity Management block contains the Low voltage Detector (LVD) and

Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1 on page 189 for further details.

7.4.1

Low voltage detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply

voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well

as the power-down keeping the ST7 in reset.

The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value

for power-on in order to avoid a parasitic reset when the MCU starts running and sinks

current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

●

VIT+(LVD) when VDD is rising

●

VIT-(LVD) when VDD is falling

The LVD function is illustrated in Figure 17.

The voltage threshold can be configured by option byte to be low, medium or high. See

Section 14.1 on page 230.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),

the MCU can only be in two modes:

●

Under full software control

●

In static safe reset

In these conditions, secure operation is always ensured for the application without the need

for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU

to reset other devices.

Note:

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur

in the application, it is recommended to pull VDD down to 0 V to ensure optimum restart

conditions. Refer to circuit example in Figure 122 on page 225 and note 4.

The LVD is an optional function which can be selected by option byte. See Section 14.1 on

page 230.

It allows the device to be used without any external RESET circuitry.

If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD

levels are not correlated. Refer to section Section 13.3.2 on page 195 and Section 13.3.3 on

page 196 for more details.

Caution:

If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will

clear the watchdog flag.

ST7LITE49K2 数据表(PDF) 47 Page - STMicroelectronics

ST7LITE49K2 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载