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ST7LITE49K2 数据表(PDF) 87 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 245 page  ST7LITE49K2 On-chip peripherals 87/245 The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value). See Figure 39. Figure 39. PWM polarity inversion The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter overflow input. ● Output control The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register. Figure 40. PWM function PWMx PWMx PIN counter overflow OPx PWMxCSR register inverter DFF TRANx ATCSR2 register DUTY CYCLE REGISTER AUTO-RELOAD REGISTER t 4095 000 WITH OE=1 AND OPx=0 (ATR) (DCRx) WITH OE=1 AND OPx=1 |
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