ST7LITE49K2 datasheet(32/245 Pages) STMICROELECTRONICS

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Data EEPROM

ST7LITE49K2

32/245

5.6

Data EEPROM read-out protection

The read-out protection is enabled through an option bit (see Section 14.1: Option bytes).

When this option is selected, the programs and data stored in the EEPROM memory are

protected against Read-out (including a re-write protection). In Flash devices, when this

protection is removed by reprogramming the option byte, the entire Program memory and

EEPROM is first automatically erased.

Note:

Both Program Memory and data EEPROM are protected using the same option bit.

Figure 9.

Data EEPROM programming cycle

5.7

EEPROM control/status register (EECSR)

Address: 0035h

Reset value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0

0: Read mode

1: Write mode

Bit 1 = E2LAT Latch access transfer bit: this bit is set by software.

It is cleared by hardware at the end of the programming cycle. It can only be cleared by

software if the E2PGM bit is cleared

Bit 0 = E2PGM Programming control and status bit

This bit is set by software to begin the programming cycle. At the end of the

programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note:

If the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

LAT

ERASE CYCLE

WRITE CYCLE

PGM

tPROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

Internal

Programming

voltage

000000

E2LAT

E2PGM

Read/write

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