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ST7LITE49K2 数据表(PDF) 90 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 245 page  On-chip peripherals ST7LITE49K2 90/245 When a break function is activated (BAx bit =1 and BREN1/BREN2 =1): ● The break pattern (PWM[3:0] bits in the BREAKCR1) is forced directly on the PWMx output pins if respective OEx is set. (after the inverter). ● The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1). ● The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1). ● ATR1, ATR2, Preload and Active DCRx are put to their reset values. ● Counters stop counting. When the break function is deactivated after applying the break (BAx bit go from 1 to 0 by software), Timer takes the control of PWM ports. Figure 43. ST7LITE49K2 block diagram of break function Output compare mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. PWM0 PWM1 PWM2 PWM3 PWM0 PWM1 PWM2 PWM3 BREAKCR1 register BREAK1 pin (Inverters) PWM0 PWM1 PWM2 PWM3 BP1EN BA1 Level Selection BR1SEL ENCNTR2 bit BREN1 bit PWM0/1 Break Enable PWM2/3 Break Enable OEx BR1EDGE Comparator1 BREAKCR2 register SWBR1 SWBR2 - - BP2EN BA2 BR2SEL BR2EDGE BREAK2 pin Comparator2 Level Selection 0 0 1 1 BREN2 bit |
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