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ST7LITE49K2 数据表(PDF) 44 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 44 Page - STMicroelectronics |
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44 / 245 page  Supply, reset and clock management ST7LITE49K2 44/245 Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte. The Reset vector fetch phase duration is 2 clock cycles. Figure 14. Reset sequence phases Table 7. CPU clock delay during Reset sequence Clock source CPU clock cycle delay Internal RC 8 MHz Oscillator 4096 Internal RC 32 kHz Oscillator 256 External clock (connected to CLKIN/PB1 pin) 4096 External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins) 4096 External Crystal/Ceramic 1-16 MHz Oscillator 4096 External Crystal/Ceramic 32 kHz Oscillator 256 RESET active phase Internal reset 256 or 4096 clock cycles Fetch vector |
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