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ST7LITE49K2 数据表(PDF) 68 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 245 page  Power saving modes ST7LITE49K2 68/245 Figure 29. Halt timing overview 1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode. Figure 30. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 18: ST7LITE49K2 interrupt mappingfor more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode. HALT RUN RUN 256 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [Active-halt disabled] HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) IBIT OFF OFF 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF X 4) ON CPU OSCILLATOR PERIPHERALS IBITS ON ON X 4) ON 256 CPU CLOCK CYCLE DELAY 5) WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 (Active-halt disabled) |
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