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ST7LITE49K2 数据表(PDF) 96 Page - STMicroelectronics

部件名 ST7LITE49K2
功能描述  Communication interfaces
PDF  245 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE49K2 数据表(HTML) 96 Page - STMicroelectronics

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How to enter one pulse mode
The steps required to enter One Pulse mode are the following:
1.
Load ATR2H/ATR2L with required value.
2.
Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3.
3.
Set OP3 in PWM3CSR if polarity change is required.
4.
Select CNTR2 by setting ENCNTR2 bit in ATCSR2.
5.
Set TRAN2 bit in ATCSR2 to enable transfer.
6.
"Wait for Overflow" by checking the OVF2 flag in ATCSR2.
7.
Select counter clock using CK<1:0> bits in ATCSR.
8.
Set OP_EN bit in PWM3CSR to enable one-pulse mode.
9.
Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced by a forced update.
Follow the same procedure for PWM2 with the bits corresponding to PWM2.
Note:
When break is applied in one-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So,
these registers have to be initialized again when break is removed.
Figure 49.
Block diagram of one pulse mode
Figure 50.
One pulse mode and PWM timing diagram
LTIC pin
Edge
Selection
OPEDGE
PWM3CSR register
OP_EN
12-bit AutoReload register 2
12-bit Upcounter 2
12-bit Active DCR2/3
Generation
PWM
OP2/3
PWM2/3
OVF
ATR2
CNTR2
LTIC
PWM2/3
000
DCR2/3
000
DCR2/3
ATR2
000
OVF
ATR2
DCR2/3
OVF
ATR2
DCR2/3
CNTR2
LTIC
PWM2/3
fcounter2
fcounter2
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.



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