ST7LITE49K2 datasheet(93/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

93/245

Figure 47.

Long range input capture block diagram

Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when

signal transition occurs, software must mask one interrupt by clearing the corresponding

ICIE bit before setting the ICS bit.

If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the

Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it

is recommended to do as follows:

First, reset both ICIE bits.

Then set the ICS bit.

Reset both ICF bits.

And then set the ICIE bit of desired interrupt.

Computing a pulse length in long Input Capture mode is not straightforward since both

timers are used. The following steps are required:

At the first Input Capture on the rising edge of the pulse, we assume that values in the

registers are the following:

–

LTICR = LT1

–

ATICRH = ATH1

–

ATICRL = ATL1

–

Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 48 on page 94.

At the second Input Capture on the falling edge of the pulse, we assume that the values

in the registers are as follows:

–

LTICR = LT2

–

ATICRH = ATH2

–

ATICRL = ATL2

–

Hence ATICR2 [11:0] = ATH2 & ATL2.

LTIC

ATIC

ICS

12-bit Input Capture register

OFF

fcpu

fLTIMER

12-bit Upcounter1

12-bit AutoReload register

8-bit Input Capture register

8-bit Timebase Counter1

fOSC/32

LTICR

CNTR1

ATICR

ATR1

8 LSB bits

12 MSB bits

LITE TIMER

12-Bit ARTIMER

cascaded

bits

32 MHz

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