ST7LITE49K2 datasheet(105/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

105/245

Timer control register 2 (ATCSR2)

Reset value: 0000 0011 (03h)

Bit 7 = FORCE2 Force counter 2 overflow bit

This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is

reset by hardware one CPU clock cycle after counter 2 overflow has occurred.

0 : No effect on CNTR2

1 : Loads FFFh in CNTR2

Note:

This bit must not be reset by software

Bit 6 = FORCE1 Force counter 1 overflow bit

This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset

by hardware one CPU clock cycle after counter 1 overflow has occurred.

0 : No effect on CNTR1

1 : Loads FFFh in CNTR1

Note:

This bit must not be reset by software

Bit 5 = ICS Input capture shorted bit

This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for

long Input Capture.

0 : ATIC for CNTR1 Input Capture

1 : LTIC for CNTR1 Input Capture

Bit 4 = OVFIE2 Overflow interrupt 2 enable bit

This bit is read/write by software and controls the overflow interrupt of counter2.

0: Overflow interrupt disabled.

1: Overflow interrupt enabled.

Bit 3 = OVF2 Overflow flag

This bit is set by hardware and cleared by software by reading the ATCSR2 register. It

indicates the transition of the counter2 from FFFh to ATR2 value.

0: No counter overflow occurred

1: Counter overflow occurred

Bit 2 = ENCNTR2 Enable counter2 for PWM2/3

This bit is read/write by software and switches the PWM2/3 operation to the CNTR2

counter. If this bit is set, PWM2/3 will be generated using CNTR2.

0: PWM2/3 is generated using CNTR1.

1: PWM2/3 is generated using CNTR2.

Note:

Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the

counter will restart from the last value.

FORCE2

FORCE1

ICS

OVFIE2

OVF2

ENCNTR2

TRAN2

TRAN1

Read/write

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