AD9544SLASHPCBZ datasheet(27/62 Pages) AD

27 / 62 page

Data Sheet

AD9544

Rev. 0 | Page 27 of 62

THEORY OF OPERATION

OVERVIEW

The AD9544 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference but

with jitter characteristics governed by the system clock, the

DCO, and the analog output PLL (APLL). The AD9544 supports

up to four reference inputs and input frequencies ranging from

1 Hz to 750 MHz. The cores of this device are two DPLLs. Each

DPLL has a programmable digital loop filter that greatly

reduces jitter transferred from the active reference to the output,

and these four DPLLs operate completely independently of each

other. The AD9544 supports both manual and automatic

holdover. While in holdover, the AD9544 continues to provide an

output as long as the system clock is present. The holdover

output frequency is a time average of the output frequency

history prior to the transition to the holdover condition. The

device offers manual and automatic reference switchover

capability if the active reference is degraded or fails completely.

The AD9544 includes a system clock multiplier and two DPLLs,

each cascaded with its own APLL.

The input signal goes first to the DPLL, which performs the

jitter cleaning and most of the frequency translation. Each DPLL

features a 48-bit DCO output that generates a signal in the range

of 162 MHz to 350 MHz.

The DCO output goes to the APLL, which multiplies the signal

up to a range of 2.424 GHz to 3.232 GHz (for Channel 0) or

3.232 GHz to 4.040 GHz (for Channel 1). After division by 2, this

signal is sent to the clock distribution section, which consists of

the 32-bit Q divider and output driver for each output. Channel 0

has six Q dividers and Channel 1 has four Q dividers.

The XOA and XOB inputs provide the input for the system clock.

These pins accept a reference clock in the 20 MHz to 300 MHz

range or a 25 MHz to 52 MHz crystal connected directly across

the XOA and XOB inputs. The system clock provides the clocks to

the frequency monitors, the DPLLs, and internal logic.

The AD9544 has five differential output drivers. Each of the five

output drivers has a dedicated 32-bit programmable Q divider.

Each differential driver operates up to 500 MHz and is configura-

ble as a CML driver with external pull-up resistors, or an HCSL

driver with external pull-down resistors. There are three drive

strengths:

•

The 7.5 mA mode is used for CML and HCSL and

ac-coupled LVDS. When used as an LVDS-compatible

driver, it must be ac-coupled and terminated with a 100 Ω

resistor across the differential pair.

•

The 15 mA mode produces a voltage swing and is compatible

with LVPECL. If LVPECL dc signal levels are required, the

designer must ac couple and rebias the AD9544 output.

The 15 mA mode can also be used with the termination

scheme shown in Figure 34 and Figure 35 to produce an

LVDS signal with the correct LVDS dc bias.

•

The 12 mA mode is halfway in between the two other settings.

REFERENCE INPUT PHYSICAL CONNECTIONS

Two pairs of pins (REFA/REFAA and REFB/REFBB) provide

access to the reference clock receivers. The user can reconfigure

each differential pair into two single-ended reference inputs. To

accommodate input signals with slow rising and falling edges,

both the differential and single-ended input receivers employ

hysteresis. Hysteresis also ensures that a disconnected or

floating input does not cause the receiver to oscillate.

When configured for differential operation, the input receivers

accommodate either ac-coupled or dc-coupled input signals.

If the input receiver is configured for dc-coupled LVDS mode,

the input receivers are capable of accepting dc-coupled LVDS

signals. The receiver is internally dc biased to handle ac-coupled

operation; however, there is no internal 50 Ω or 100 Ω termination.

AD9544/PCBZ 数据表(PDF) 27 Page - Analog Devices

AD9544/PCBZ 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载