AD9544SLASHPCBZ datasheet(46/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 46 of 62

WATCHDOG TIMER

The watchdog timer is a general-purpose programmable timer

capable of triggering a specific IRQ event (see Figure 48). The

timer relies on the system clock, however; therefore, the system

clock must be present and locked for the watchdog timer to be

functional. The bit fields associated with the watchdog timer

reside in the Mx pin status and control function section of the

The user sets the period of the watchdog timer by programming

the watchdog timer (ms) bit field with a 16-bit timeout value. A

nonzero value sets the timeout period in units of milliseconds,

providing a range of 1 ms to 65.535 sec, whereas a zero value

(0x0000, the default value) disables the timer. The relative accuracy

of the timer is approximately 0.1% with an uncertainty of

0.5 ms. Note that whenever the user writes a 16-bit timeout

value to the watchdog timer, it automatically clears the timer,

ensuring a correct timeout period (per the new value) starting

from the moment of the bit field update.

The watchdog timer (ms) bit field relates to the timeout period

as follows:

Watchdog Timer (ms) = Timeout Period × 103

To determine the value of the watchdog timer (ms) bit field

necessary for a timeout period of 10 sec,

Watchdog Timer (ms) = Timeout Period × 103

= 10 × 103

= 10,000

= 0x2710 (hexadecimal)

If enabled, the timer runs continuously and generates a timeout

IRQ event when the timeout period expires. The user has access

to the watchdog timer status via its associated IRQ monitor bit

or by assigning it directly to an Mx status pin. In the case of an

Mx status pin, the timeout event of the watchdog timer is a

pulse spanning 96 system clock periods (approximately 40 ns).

There are two ways to reset the watchdog timer, thereby preventing

it from indicating a timeout event. The first method is by

writing a Logic 1 to the clear watchdog bit (an autoclearing bit)

in the operational controls section of the register map.

Alternatively, the user can program any of the multifunction

pins as a control pin to reset the watchdog timer, which allows

the user to reset the timer by means of a hardware pin rather

than using the serial port.

There are two typical cases for employing the watchdog timer.

Both cases assume that the watchdog timer output appears at

the output of an appropriately configured Mx status pin (the

watchdog timer output for the following case descriptions). The

first case is for an external device (for example, an FPGA or

microcontroller) to monitor the watchdog timer output using it

as a signal to carry out periodic housekeeping functions. The

second case is to have the watchdog timer output connected to

the external device, such that the assertion of the watchdog

output resets the external device. In this way, under normal

operation, the external device repeatedly resets the watchdog

timer by either writing Logic 1 to the clear watchdog bit or by

asserting an Mx control pin configured for clearing the watchdog.

In this way, as long as the external device keeps resetting the

watchdog timer before it times out, the watchdog timer does

not generate an output signal. As such, the watchdog timer does

not reset the external device. However, if the external device

fails to reset the watchdog timer before its timeout period

expires, the watchdog timer eventually times out, resetting the

external device via the appropriately configured Mx status pin.

TIMER

CLK

OUT

1kHz

PRESET

BIT D7

CLEAR

Mx PIN FUNCTION LOGIC

Mx PINS

40ns

TO IRQ EVENT

SOURCE LOGIC

CLEAR

WATCHDOG

VIA Mx PIN

WATCHDOG

OUTPUT VIA

Mx PIN

CLEAR

WATCHDOG

TIMER (MS)

TEXT

= BIT(S) IN THE REGISTER MAP

Figure 48. Watchdog Timer

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