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AD9544/PCBZ 数据表(PDF) 36 Page - Analog Devices

部件名 AD9544/PCBZ
功能描述  Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9544/PCBZ 数据表(HTML) 36 Page - Analog Devices

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AD9544
Data Sheet
Rev. 0 | Page 36 of 62
START TIMEOUT CLOCK:
TIME = 0
CAL_COUNT = 0
LOCK REG BIT 3 = 1
TIMEOUT CLOCK:
TIME > 50ms
CAL_COUNT > 1
NO
YES
NO
YES
NO
YES
CAL_COUNT =
CAL_COUNT + 1
APLL LOCK
DETECT POLLING
LOOP
APLL RECALIBRATION
LOOP
START
END
END
(TO RST_COUNT
CHECK)
WRITE:
CAL REG BIT 1 = 0
WRITE:
REGISTER 0x000F BIT 0 = 1
WRITE:
REGISTER 0x000F BIT 0 = 1
WRITE:
CAL REG BIT 1 = 1
VCO
CALIBRATION
OPERATION
WRITE:
SYNC REG BIT 3 = 1
WRITE:
REGISTER 0x000F BIT 0 = 1
WRITE:
REGISTER 0x000F BIT 0 = 1
MANUAL
DISTRIBUTION
SYNCHRONIZATION
OPERATION
WRITE:
SYNC REG BIT 3 = 0
AUTOSYNC
REGISTERS
BITS[1:0] = 0
NO
YES
CAL REG.
0x2100
0x2200
APLL
0
1
LOCK REG.
0x3100
0x3200
SYNC REG.
0x2101
0x2201
AUTOSYNC REG.
0x10DB
0x14DB
Figure 44. System Clock Initialization Subprocess



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