AD9544SLASHPCBZ datasheet(56/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 56 of 62

SERIAL CONTROL PORT

The AD9544 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9544 serial control port is compatible with most

synchronous transfer formats, including I²C, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9544 register map.

The AD9544 uses the Analog Devices unified SPI protocol (see

the Analog Devices Serial Control Interface Standard). The

unified SPI protocol guarantees that all new Analog Devices

products using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

Unified SPI differs from the SPI port found on older Analog

Devices products, such as the AD9557 and AD9558, in the

following ways:

•

Unified SPI does not have byte counts. A transfer is

terminated when the CSB pin goes high. The W1 and W0

bits in the traditional SPI become the A12 and A13 bits of

the register address. This is similar to streaming mode in

the traditional SPI.

•

The address ascension bit (Register 0x000) controls

whether register addresses are automatically incremented

or decremented regardless of the LSB/MSB first setting. In

traditional SPI, LSB first mode dictated auto-incrementing

and MSB first mode dictated auto-decrementing of the

•

The first 16 register addresses of devices that adhere to the

unified serial port have a consistent structure.

SPI/I²C PORT SELECTION

Although the AD9544 supports both the SPI and I2C serial port

protocols, only one is active following power-up (as determined

by the M4 multifunction pin during the start-up sequence). The

only way to change the serial port protocol is to reset (or power

cycle) the device. See Table 27 for the I2C address assignments.

SPI SERIAL PORT OPERATION

Pin Descriptions

The serial clock (SCLK) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 50 MHz.

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB first

and LSB first data formats. Both the hardware configuration

and data format features are programmable. The 3-wire mode

uses the serial data input/output (SDIO) pin for transferring

data in both directions. The 4-wire mode uses the SDIO pin

for transferring data to the AD9544, and the SDO pin for

transferring data from the AD9544.

The chip select (CSB) pin is an active low control that gates read

and write operations. Assertion (active low) of the CSB pin

initiates a write or read operation to the AD9544 SPI port. The

user can transfer any number of data bytes in a continuous stream.

The register address is automatically incremented or decremented

based on the setting of the address ascension bit (Register 0x00).

The user must deassert the CSB pin following the last byte

transferred, thereby ending the stream mode. This pin is

internally connected to a 10 kΩ pull-up resistor. When CSB is

high, the SDIO and SDO pins enter a high impedance state.

Implementation Specific Details

The Analog Devices Serial Control Interface Standard provides

a detailed description of the unified SPI protocol and covers

items such as timing, command format, and addressing. The

unified SPI protocol defines the following device specific items:

•

Analog Devices unified SPI protocol revision: 1.0

•

Chip type: 0x5

•

Product ID: 0x012

•

Physical layer: 3-wire and 4-wire supported and 1.5 V,

1.8 V, and 2.5 V operation supported

•

Optional single-byte instruction mode: not supported

•

Data link: not used

•

Control: not used

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two-part communication

cycle. The first part is a 16-bit instruction word coincident with

the first 16 SCLK rising edges. The second part is the payload,

the bits of which are coincident with SCLK rising edges. The

instruction word provides the AD9544 serial control port with

information regarding the payload. The instruction word

includes the R/W bit that indicates the direction of the payload

transfer (that is, a read or write operation). The instruction

word also indicates the starting register address of the first

payload byte.

Write

When the instruction word indicates a write operation, the

payload is written into the serial control port buffer of the

AD9544. Data bits are registered on the rising edge of SCLK.

Generally, it does not matter what data is written to blank

registers; however, it is customary to use 0s. Note that the user

must verify that all reserved registers within a specific range

have a default value of 0x00; however, Analog Devices makes

every effort to avoid having reserved registers with nonzero

default values.

Most of the serial port registers are buffered; therefore, data

written into buffered registers does not take effect immediately.

To transfer buffered serial control port contents to the registers

that actually control the device requires an additional operation,

an IO_UPDATE operation, implemented in one of two ways.

One is to write a Logic 1 to Register 0x0F, Bit 0 (this bit is an

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