AD9544SLASHPCBZ datasheet(7/62 Pages) AD

7 / 62 page

Data Sheet

AD9544

Rev. 0 | Page 7 of 62

REFERENCE INPUTS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Differential mode specifications assume ac coupling

of the input signal to the reference input pins

Frequency Range

Sinusoidal Input

750

MHz

Lower limit dependent on input slew rate

LVPECL Input

750 × 106

Lower limit dependent on ac coupling; 1 Hz is

equivalent to 1 pulse per second (pps)

LVDS Input

500 × 106

Assumes an LVDS minimum of 494 mV p-p differential

amplitude; lower limit dependent on ac coupling

Slew Rate for Sinusoidal input

V/µs

Minimum input slew rate for device operation; jitter

degradation may occur for slew rates < 35 V/µs

Common-Mode Input Voltage

0.64

Internally generated self bias voltage

Differential Input Amplitude

Peak-to-peak differential voltage swing across pins

required to ensure switching between logic levels as

measured with a differential probe; instantaneous

voltage on either pin must not exceed 1.3 V

fIN < 500 MHz

350

2100

mV p-p

fIN = 500 MHz to 750 MHz

500

2100

mV p-p

Differential Input Voltage Hysteresis

100

Input Resistance

kΩ

Equivalent differential input resistance

Input Pulse Width

LVPECL

600

LVDS

900

DC-COUPLED, LVDS-COMPATIBLE

MODE

Applies for dc-coupling to an LVDS source

Frequency Range

450 × 106

Common-Mode Input Voltage

1.125

1.375

Differential Input Amplitude

400

1200

mV p-p

Differential voltage across pins required to ensure

switching between logic levels; instantaneous

voltage on either pin must not exceed the supply rails

Differential Input Voltage Hysteresis

100

Input Resistance

kΩ

Input Pulse Width

SINGLE-ENDED MODE

Single-ended mode specifications assume dc

coupling of the input signal to the reference input

pins

Frequency Range

1.2 V AC-Coupled

500 × 106

Lower limit dependent on ac-coupling

1.2 V and 1.8 V CMOS

500 × 106

CMOS specifications assume dc coupling of the input

signal to the reference input pins

1.2 V AC-Coupled Common-Mode

Voltage

610

Internally generated self-bias voltage

Input Amplitude (Single-Ended,

AC-Coupled Mode)

360

1200

mV p-p

Peak-to-peak single-ended voltage swing;

instantaneous voltage must not exceed 1.3 V

1.2 V and 1.8 V CMOS Input

Voltage

High, VIH

0.65 × VREF

1.15 × VREF

VREF is determined by operating mode of the CMOS

input receiver, 1.2 V or 1.8 V

Low, VIL

0.35 × VREF

Input Resistance

DC-Coupled Single-Ended Mode

kΩ

AC-Coupled Single-Ended Mode

kΩ

Input Pulse Width

900

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AD9544/PCBZ 数据表(PDF) 7 Page - Analog Devices

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