AD9544SLASHPCBZ datasheet(60/62 Pages) AD

60 / 62 page

AD9544

Data Sheet

Rev. 0 | Page 60 of 62

When all the data bytes are read or written, stop conditions are

established. In write mode, the master device (transmitter)

asserts a stop condition to end data transfer during the clock

pulse following the acknowledge bit for the last data byte from the

slave device (receiver). In read mode, the master device (receiver)

receives the last data byte from the slave device (transmitter)

but does not pull SDA low during the ninth clock pulse (a

nonacknowledge bit). By receiving the nonacknowledge bit, the

slave device knows that the data transfer is finished and enters

idle mode. The master device then takes the data line low

during the low period before the 10th clock pulse, and high

during the 10th clock pulse to assert a stop condition.

A start condition can be used instead of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

SDA

START CONDITION

STOP CONDITION

SCL

Figure 60. Start and Stop Conditions

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

Figure 61. Acknowledge Bit

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

3 TO 7

ACK FROM

MASTER RECEIVER

NONACK FROM

MASTER RECEIVER

SDA

SCL

Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave

AD9544/PCBZ 数据表(PDF) 60 Page - Analog Devices

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AD9544/PCBZ 数据表(PDF) 60 Page - Analog Devices

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