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AD9544/PCBZ 数据表(PDF) 53 Page - Analog Devices

部件名 AD9544/PCBZ
功能描述  Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9544/PCBZ 数据表(HTML) 53 Page - Analog Devices

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Data Sheet
AD9544
Rev. 0 | Page 53 of 62
Register Transfer Instructions (0x00 to 0x7F)
Instructions with a hexadecimal value from 0x00 through 0x7F
indicate a register transfer operation. Register transfer instructions
require a 2-byte suffix, which constitutes the starting address of
the AD9544 register targeted for transfer (where the first byte
to follow the data instruction is the most significant byte of the
register address). When the EEPROM controller encounters a
data instruction, it knows to interpret the next two bytes as the
register map target address.
Note that the value of the register transfer instruction encodes
the payload length (number of bytes). That is, the EEPROM
controller knows how many register bytes to transfer to/from
the indicated register by adding 1 to the instruction value. For
example, Data Instruction 0x1A has a decimal value of 26;
therefore, the controller knows to transfer 27 bytes to and from
the target register (that is, one more than the value of the
instruction).
Input/Output Update Instruction (0x80)
When the EEPROM controller encounters an input/output
update instruction during an upload sequence, it stores the
instruction in EEPROM. When encountered during a download
sequence, however, the EEPROM controller initiates an
input/output update event (equivalent to the user asserting the
IO_UPDATE bit in the serial port section of the register map).
Device Action Instructions (0x90 to 0xAF)
When the EEPROM controller encounters a device action
instruction during an upload sequence, it stores the instruction
in EEPROM. When encountered during a download sequence,
however, the EEPROM controller executes the specified action
per Table 31.
Conditional Instructions (0xB0 to 0xBF)
The conditional instructions allow conditional execution of
EEPROM instructions during a download sequence. During an
upload sequence, however, they are stored as is and have no
effect on the upload process.
Conditional processing makes use of four elements:
The conditional instruction.
The condition value.
The condition ID.
The condition map.
Conditional Instruction
When the EEPROM controller encounters a conditional
instruction during an upload sequence, it stores the instruction
in the EEPROM. When the EEPROM controller detects a
conditional instruction during a download sequence, it affects
the condition map as well as the outcome of conditional processing.
Condition Value
The condition value has a one to one correspondence to the
conditional instruction. Specifically, the condition value is the
value of the conditional instruction minus 0xB0. Therefore,
condition values have a range of 0 to 15. The EEPROM controller
uses condition values in conjunction with the condition map,
while the user uses a condition value to populate the EEPROM
load condition bit field of the register map with a condition ID.
Condition ID
The condition ID is the value stored in the 4-bit EEPROM load
condition bit field in the EEPROM section of the register map.
The EEPROM controller uses the condition ID in conjunction
with the condition map to determine which instructions to
execute or ignore during a download sequence.
Condition Map
The condition map is a table maintained by the EEPROM
controller consisting of a list of condition values. When the
EEPROM controller encounters a conditional instruction
during a download sequence, it determines the corresponding
condition value of the instruction (0 to 15). If the condition
value is nonzero, the EEPROM controller places the condition
value in the condition map. Conversely, if the condition value
is zero, the controller clears the condition map and applies
Condition 0. Condition 0 causes all subsequent instructions to
execute unconditionally (until the controller encounters a new
conditional instruction that causes conditional processing).
Conditional Processing
While executing a download sequence, the EEPROM controller
executes or skips instructions depending on the condition ID
and the contents of the condition map (except for the condi-
tional and end of data instructions, which always execute
unconditionally).
If the condition map is empty or the condition ID is zero, all
instructions execute unconditionally during download. However,
if the condition ID is nonzero and the condition map contains a
condition value matching the condition ID, the EEPROM
controller executes the subsequent instructions. Alternatively,
if the condition ID is nonzero but the condition map does not
contain a condition value matching the condition ID, the
EEPROM controller skips instructions until it encounters a
conditional instruction with a condition value of zero or a
condition value matching the condition ID.
Note that the condition map allows multiple conditions to exist
at any given moment. This multiconditional processing mecha-
nism enables the user to have one download instruction sequence
with many possible outcomes, depending on the value of the
condition ID and the order in which the controller encounters
conditional instructions. An example of the use of conditional
processing is shown in Table 32.



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