AD9544SLASHPCBZ datasheet(51/62 Pages) AD

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Data Sheet

AD9544

Rev. 0 | Page 51 of 62

EEPROM USAGE

OVERVIEW

The AD9544 supports an external, I2C-compatible, EEPROM

with dedicated access. With some restrictions, the AD9544 also

supports multidevice access to a single external EEPROM on a

shared I2C common bus. The AD9544 has an on-chip I2C

master to interface to the EEPROM through the Mx pins.

Because the default register settings of the AD9544 do not

define a particular frequency translation, the user must factory

program the EEPROM content before it can be downloaded to

the register map (either automatically or manually). If desired,

the user can store custom device configurations by manually

forcing an upload to the EEPROM via the register map.

EEPROM CONTROLLER GENERAL OPERATION

EEPROM Controller

The EEPROM controller governs all aspects of communication

with the EEPROM. Because the I2C interface uses a 100 kHz

(normal mode) or 400 kHz (fast mode) communication link,

the controller runs synchronous to an on-chip generated clock

source suitable for use as the I2C serial clock. The on-chip oscillator

enables asynchronously immediately on a request for activation

of the controller. When the oscillator starts, it notifies the

controller of its availability, and the controller activates. After

the requested controller operation is complete, the controller

disables the clock generator and returns to an idle state.

EEPROM Download

An EEPROM download transfers contents from the EEPROM

to the AD9544 programming registers and invokes specific

actions per the instructions stored in the EEPROM (see Table 31).

Automatic downloading is the most common method for

initiating an EEPROM download sequence, which initiates at

power-up of the AD9544, provided Pin M3 is Logic 1 at power-

up (see the Multifunction Pins at Reset/Power-Up section).

Alternatively, instead of cycling power to the AD9544 to initiate an

EEPROM download, the user can force the RESETB pin to

Logic 0, force Pin M3 to Logic 1, and then return the RESETB

pin to Logic 1 and remove the drive source from Pin M3.

The user can also request an EEPROM download on demand

(that is, without resetting or cycling power to the AD9544) by

writing a Logic 1 to the EEPROM load bit in the EEPROM

section of the register map.

Note that the load from EEPROM bit does not require an

input/output update. Writing a Logic 1 to this bit immediately

triggers a download sequence.

The EEPROM controller sets the EEPROM load in progress bit

(in the general status section of the register map) to Logic 1

while the download sequence is in progress as an indication to

the user that the controller is busy.

EEPROM Upload

To store the AD9544 register contents in the EEPROM, the user

must write a Logic 1 to the EEPROM save bit in the EEPROM

section of the register map. The EEPROM save bit does not

require an input/output update. Writing a Logic 1 to this bit

immediately triggers an upload sequence.

The AD9544 has the equivalent of a write protect feature in that

the user must write a Logic 1 to the EEPROM write enable bit

(in the EEPROM section of the register map) prior to requesting an

upload to the EEPROM. Attempting to upload to the EEPROM

without first setting the EEPROM write enable bit results in a

fault indication (that is, the AD9544 asserts the EEPROM fault bit

in the general status section of the register map).

A prerequisite to an EEPROM upload is the existence of an upload

sequence stored in the 15-byte EEPROM sequence section of

the register map. That is, the user must store a series of upload

instructions (see the EEPROM Instruction Set section) in the

EEPROM sequence section of the register map prior to executing

an EEPROM upload.

The EEPROM controller performs an upload sequence by reading

the instructions stored in the EEPROM sequence section of the

the data stored in the EEPROM sequence section of the register

map are instructions to the EEPROM controller on what to

store in the EEPROM (including operational commands and

AD9544 register data).

Note that the EEPROM controller sets the EEPROM save in

progress bit (in the status readback section of the register map)

to Logic 1 while the upload sequence is in progress as an indication

to the user that the controller is busy.

Because the EEPROM sequence section of the register map is

only 15 bytes, it typically cannot hold enough instructions to

upload a complete set of AD9544 data to the EEPROM. Therefore,

most upload sequences necessitate that the user upload a series

of subsequences. For example, to accomplish a required upload

sequence consisting of 20 bytes of instructions, perform the

following procedure:

Write the first 14 instructions to the EEPROM sequence

registers in the EEPROM section of the register map, with

the 15th instruction being a pause instruction (see Table 31).

Initiate an EEPROM upload by writing Logic 1 to the

EEPROM save bit. When the EEPROM controller reaches

the pause instruction, it suspends the upload process and

waits for another assertion of the EEPROM save bit.

While the controller pauses, write the remaining six bytes

of the upload sequence into the EEPROM sequence

registers in the EEPROM section of the register map,

followed by an end of data instruction (see Table 31).

Initiate an EEPROM upload by writing Logic 1 to the

EEPROM save bit. When the EEPROM controller reaches

the end of data instruction, it terminates the upload process.

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