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AD9544/PCBZ 数据表(PDF) 15 Page - Analog Devices |
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AD9544/PCBZ 数据表(HTML) 15 Page - Analog Devices |
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15 / 62 page  Data Sheet AD9544 Rev. 0 | Page 15 of 62 Parameter Min Typ Max Unit Test Conditions/Comments Channel 1—DPLL1, APLL1 Channel 0 powered down RMS Jitter (12 kHz to 20 MHz) Configuration 1—155.52 MHz 247 fs Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 38.88 MHz, fVCO = 3265.92 MHz, fOUT = 155.52 MHz, BWDPLL = 50 Hz, phase buildout operation, half divide enabled Configuration 2—245.76 MHz 280 fs Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 30.72 MHz, fVCO = 3686.4 MHz, fOUT = 245.76 MHz, BWDPLL = 50 Hz, half divide enabled, internal zero delay operation Configuration 3—491.52 MHz 323 fs Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz TCXO, BWCOMP = 50 Hz, fREF = 1 Hz, fVCO = 3932.16 MHz, fOUT = 491.52 MHz, BWDPLL = 50 mHz, phase buildout operation Configuration 4—125 MHz 243 fs Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz TCXO, BWCOMP = 50 Hz, fREF = 125 MHz, fVCO = 3250 MHz, fOUT = 125 MHz, BWDPLL = 0.1 Hz, phase buildout operation Configuration 5—312.5 MHz 266 fs Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 25 MHz, fVCO = 3750 MHz, fOUT = 312.5 MHz, BWDPLL = 50 Hz, phase buildout operation Configuration 6—174.7030837 MHz 264 fs Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 155.52 MHz, fVCO = 3319.3586 MHz, fOUT = (155.52 × 255/227) MHz, BWDPLL = 50 Hz, phase buildout operation PHASE NOISE Table 22. Parameter Min Typ Max Unit Test Conditions/Comments PHASE NOISE System clock doubler enabled; high phase margin mode enabled; there is not a significant jitter difference between driver modes Channel 0—DPLL0, APLL0 Channel 1 powered down RMS Jitter (12 kHz to 20 MHz) Configuration 1—155.52 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 38.88 MHz, fVCO = 2488.32 MHz, fOUT = 155.52 MHz, BWDPLL = 50 Hz, phase buildout operation 10 Hz Offset −81 dBc/Hz 100 Hz Offset −98 dBc/Hz 1 kHz Offset −118 dBc/Hz 10 kHz Offset −128 dBc/Hz 100 kHz Offset −134 dBc/Hz 1 MHz Offset −144 dBc/Hz 10 MHz Offset −158 dBc/Hz Floor −161 dBc/Hz Configuration 2—245.76 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 30.72 MHz, fVCO = 2457.6 MHz, fOUT = 245.76 MHz, BWDPLL = 50 Hz, internal zero delay operation 10 Hz Offset −77 dBc/Hz 100 Hz Offset −93 dBc/Hz 1 kHz Offset −114 dBc/Hz 10 kHz Offset −125 dBc/Hz 100 kHz Offset −130 dBc/Hz 1 MHz Offset −140 dBc/Hz 10 MHz Offset −156 dBc/Hz Floor −161 dBc/Hz |
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