AD9544SLASHPCBZ datasheet(38/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 38 of 62

STATUS AND CONTROL PINS

The AD9544 features seven independently configurable digital

CMOS status/control pins (M0 to M6). Configuring an Mx pin

as a status pin causes that pin to be an output. Conversely,

configuring an Mx pin as a control pin causes that pin to be an

input. Register 0x0102 to Register 0x0108 control both the

nature of the pin (either status or control via Bit D7), as well as

the selection of the status source or control destination

associated with the pin via Bits[D6:D0]. During power-up or

reset, the Mx pins temporarily become inputs and only allow the

device to autoconfigure. Figure 46 is a block diagram of the Mx pin

functionality.

The Mx pin control logic uses special register write detection

logic to prevent these pins from behaving unpredictably when the

Mx pin function changes, especially when changing mode from

input to output or vice versa.

When an Mx pin functions as an output, it continues operating

according to the prior function, even after the user programs

the corresponding registers. However, assertion of an input/output

update causes the corresponding pins to switch to the new

function according to the newly programmed register contents.

Note that changing from one output function to another output

function on an Mx pin does not require special timing to avoid

input/output contention on the pin.

When an Mx pin functions as an input, programming a particular

Mx pin function register causes all the Mx pin control functions

to latch their values. Assertion of an input/output update

switches to the newly programmed pin function, at which time

normal behavior resumes. Note that, when switching from one

input function to another input function on the same pin, the

logic state driven at the input to the pin can change freely

during the interval between writing the new function to the

corresponding register and asserting the input/output update.

When switching the operation of an Mx pin from an input to an

output function, the recommendation is that the external drive

source become high impedance during the interval between

writing the new function and asserting the input/output update.

When switching the operation of an Mx pin from an output to

an input, the recommendation is as follows. First, program the

Mx pin input function to no operation (NOOP) and assert the

input/output update. This configuration avoids input/output

contention on the Mx pin or other undesired behavior because,

prior to the assertion of the input/output update, the device

continues to drive the Mx pin. Following the assertion of the

input/output update, the device releases the Mx pin but ignores

the logic level on the pin due to the programmed NOOP function.

Note that the recommendation is to avoid using a high impedance

source on an Mx pin configured as an input because this may

cause excessive internal current consumption. Second, drive the

Mx pin with Logic 0 or Logic 1 via the desired external source

and program the associated Mx pin register from NOOP to the

desired function.

CONTROL

FUNCTION

SELECT

STATUS

SOURCE

SELECT

Mx PIN

CONTROL

REGISTERS

I/O UPDATE

I/O

CONTROL

DEVICE

RESET

POWER UP

AUTOCONFIGURATION

CONTROL

DESTINATIONS

STATUS

SOURCES

Mx PIN FUNCTION LOGIC

Figure 46. Mx Pin Logic

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