AD9544SLASHPCBZ datasheet(5/62 Pages) AD

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Data Sheet

AD9544

Rev. 0 | Page 5 of 62

SPECIFICATIONS

The minimum and maximum values apply for the full range of the supply voltage and operating temperature variations. The typical

values apply for VDD = 1.8 V and TA = 25°C, unless otherwise noted.

SUPPLY VOLTAGE

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDDIOA, VDDIOB

1.71

1.8

3.465

1.8 V, 2.5 V, and 3.3 V operation supported

VDD

1.71

1.8

1.89

SUPPLY CURRENT

The maximum supply voltage values given in Table 1 are the basis for the maximum supply current specifications. The typical supply

voltage values given in Table 1 are the basis for the typical supply current specifications. The minimum supply voltage values given in

Table 1 are the basis for the minimum supply current specifications.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT FOR TYPICAL

CONFIGURATION

The Typical Configuration specification in Table 3 is the basis for

the values shown in this section

IVDDIOx

Aggregate current for all VDDIOx pins (where x = A or B)

IVDD

260

310

355

Aggregate current for all VDD pins

SUPPLY CURRENT FOR ALL BLOCKS

RUNNING CONFIGURATION

The All Blocks Running condition in Table 3 is the basis for the

values shown in this section

IVDDIOx

Aggregate current for all VDDIOx pins (where x = A or B)

IVDD

321

390

430

Aggregate current for all VDD pins

POWER DISSIPATION

The typical values apply for VDD = 1.8 V, and the maximum values apply for VDD = 1.89 V.

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

Typical Configuration

445

560

671

System clock = 49.152 MHz crystal; two DPLLs active;

two 19.44 MHz input references in differential mode;

two ac-coupled PLL0 CML output drivers at 245.76 MHz;

and two PLL1 CML output drivers at 156.25 MHz

All Blocks Running

548

700

813

System clock = 49.152 MHz crystal; two DPLLs active;

two 19.44 MHz input references in differential mode;

three ac-coupled PLL0 HCSL output drivers at 400 MHz; and

two PLL1 HCSL output drivers at 400 MHz

Full Power-Down

125

Based on the Typical Configuration specification with the

power down all bit set to Logic 1

Incremental Power Dissipation

Based on the Typical Configuration specification; the values in this

section indicate the change in power due to the indicated

operation relative to the Typical Configuration specification

Complete DPLL/APLL On/Off

200

Change in dissipated power relative to the Typical Configuration

specification; the blocks, powered down, consist of one reference

input, one DPLL, one APLL, two channel dividers, and two

output drivers

Incremental Power Dissipation

Complete DPLL/APLL On/Off

200

Based on the Typical Configuration specification; the values in

this section indicate the change in power due to the indicated

operation relative to the Typical Configuration specification;

the blocks, powered down, consist of one reference input, one

DPLL, one APLL, two channel dividers, and two output drivers

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