AD9544SLASHPCBZ datasheet(39/62 Pages) AD

39 / 62 page

Data Sheet

AD9544

Rev. 0 | Page 39 of 62

MULTIFUNCTION PINS AT RESET/POWER-UP

At power-up or in response to a reset operation, the Mx pins

enter a special operating mode. For a brief interval following a

power-up or reset operation, the Mx pins function only as

inputs (the internal drivers enter a high impedance state during

a power-up/reset operation). During this brief interval, the

device latches the logic levels at the Mx inputs and uses this

information to autoconfigure the device accordingly. The Mx

pins remain high-Z until either an EEPROM operation occurs,

in which case M1 or M2 become an I2C master, or the user (or

EEPROM) programs them to be outputs.

If the user does not connect external pull-up/pull-down resistors

to the Mx pins, the M3 and M4 pins have internal pull-down

resistors to ensure a predictable start-up configuration. In the

absence of external resistors, the internal pull-down resistors

ensure that the device starts up with the serial port in SPI mode

and without automatically loading data from an external EEPROM

(see Table 26). Although the M0, M1, M2, M5, and M6 pins are

high impedance at startup, connect external 100 kΩ pull-down

or pull-up resistors to these pins to ensure robust operation.

The Mx pin start-up conditions are shown in Table 26. M0, M1,

and M2 are excluded from Table 26 because these pins have no

explicit function during a power-up or reset operation.

Table 26. Mx Pin Function at Startup or Reset

Startup/Reset

Function

Logic 1

Logic 0

EEPROM load

function

Load from

EEPROM

Do not load from

EEPROM (default)

Serial port

function

I²C mode

SPI mode

(default)

I2C address offset

See Table 27

I2C address offset

See Table 27

When the start-up conditions select the serial port to be I2C

mode (that is, M4 is Logic 1 at startup), the M5 and M6 pins

determine the I2C port device address offset per Table 27. Note

that the logic levels in Table 27 only apply during a power-up or

reset operation.

Table 27. I²C Device Address Offset

Address Offset

Not applicable

1001000 (0x48)

1001001 (0x49)

1001010 (0x4A)

1001011 (0x4B)

1 X means don’t care.

STATUS FUNCTIONALITY

Configuring an Mx pin as a status pin gives the user access to

specific internal device status/IRQ functions in the form of a

hardware pin that produces a logic signal. Each Mx pin has a

corresponding Mx function register. To assign an Mx pin as a

status pin, write a Logic 1 to the Mx output enable bit in the

corresponding Mx pin function register.

To assign a specific status/IRQ function to an Mx pin configured

as a status pin, program the appropriate 7-bit code (see Table 30)

to Bits[D6:D0] of the corresponding Mx function register.

See the Interrupt Request (IRQ) section for details regarding

IRQ functionality.

When configured as a status pin, the output mode of an Mx pin

depends on a 2-bit mode code per Table 28. The 2-bit codes reside

in Register 0x0100 through Register 0x0101, where the 2-bit

codes constitute the Mx receiver/driver bit fields. Note that the

Mx receiver/driver bit fields perform a different function when

the Mx pin is a control pin (see the Control Functionality

section).

Table 28. Mx Receiver/Driver Bit Field Codes for Mx Status Pins

Code

Mode

Description

CMOS,

active high

Output is Logic 0 when deasserted and

Logic 1 when asserted (default operating

mode).

CMOS,

active low

Output is Logic 1 when deasserted and

Logic 0 when asserted.

PMOS,

open drain

Output is high impedance when deasserted

and active high when asserted.

NMOS,

open drain

Output is high impedance when deasserted

and active low when asserted.

The PMOS open-drain mode requires an external pull-down

resistor. The NMOS open-drain mode requires an external pull-up

resistor. Note that the open-drain modes enable the implementa-

tion of wire-OR’ed functionality of multiple Mx status pins

(including Mx status pins across multiple AD9544 devices or other

compatible devices—for example, to implement an IRQ bus).

The drive strength of an Mx status pin is programmable via the

corresponding Mx configuration bits (Bits[D6:D0] of the pin

drive strength register). Logic 0 (default) selects normal drive

strength (~6 mA) and Logic 1 selects weak drive strength (~3 mA).

CONTROL FUNCTIONALITY

Configuring an Mx pin as a control pin gives the user control of

the specific internal device functions via an external hardware

logic signal. Each Mx pin has a corresponding Mx function register.

To assign an Mx pin as a control pin, write a Logic 0 to the

Mx output enable bit in the corresponding Mx function register.

To assign an Mx control pin to a specific function, program the

appropriate 7-bit code (see Table 30) to Bits[D6:D0] of the

corresponding Mx function register. See the Interrupt Request

(IRQ) section for details regarding IRQ functionality.

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