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AD9544/PCBZ 数据表(PDF) 17 Page - Analog Devices |
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AD9544/PCBZ 数据表(HTML) 17 Page - Analog Devices |
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17 / 62 page  Data Sheet AD9544 Rev. 0 | Page 17 of 62 Parameter Min Typ Max Unit Test Conditions/Comments Channel 1—DPLL1, APLL1 Channel 0 powered down RMS Jitter (12 kHz to 20 MHz) Configuration 1—155.52 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 38.88 MHz, fVCO = 3265.92 MHz, fOUT = 155.52 MHz, BWDPLL = 50 Hz, phase buildout operation, half divide enabled 10 Hz Offset −81 dBc/Hz 100 Hz Offset −98 dBc/Hz 1 kHz Offset −118 dBc/Hz 10 kHz Offset −128 dBc/Hz 100 kHz Offset −132 dBc/Hz 1 MHz Offset −144 dBc/Hz 10 MHz Offset −158 dBc/Hz Floor −162 dBc/Hz Configuration 2—245.76 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 30.72 MHz, fVCO = 3686.4 MHz, fOUT = 245.76 MHz, BWDPLL = 50 Hz, half divide enabled; internal zero delay operation 10 Hz Offset −76 dBc/Hz 100 Hz Offset −93 dBc/Hz 1 kHz Offset −114 dBc/Hz 10 kHz Offset −124 dBc/Hz 100 kHz Offset −127 dBc/Hz 1 MHz Offset −138 dBc/Hz 10 MHz Offset −156 dBc/Hz Floor −161 dBc/Hz Configuration 3—491.52 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz TCXO, BWCOMP = 50 Hz, fREF = 1 Hz, fVCO = 3932.16 MHz, fOUT = 491.52 MHz, BWDPLL = 50 mHz, phase buildout operation 10 Hz Offset −74 dBc/Hz 100 Hz Offset −90 dBc/Hz 1 kHz Offset −108 dBc/Hz 10 kHz Offset −118 dBc/Hz 100 kHz Offset −120 dBc/Hz 1 MHz Offset −131 dBc/Hz 10 MHz Offset −150 dBc/Hz Floor −160 dBc/Hz Configuration 4—125 MHz Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz TCXO, BWCOMP = 50 Hz, fREF = 125 MHz, fVCO = 3250 MHz, fOUT = 125 MHz, BWDPLL = 0.1 Hz, phase buildout operation 10 Hz Offset −83 dBc/Hz 100 Hz Offset −106 dBc/Hz 1 kHz Offset −120 dBc/Hz 10 kHz Offset −131 dBc/Hz 100 kHz Offset −135 dBc/Hz 1 MHz Offset −145 dBc/Hz 10 MHz Offset −160 dBc/Hz Floor −163 dBc/Hz |
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