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AD9544/PCBZ 数据表(PDF) 13 Page - Analog Devices

部件名 AD9544/PCBZ
功能描述  Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9544/PCBZ 数据表(HTML) 13 Page - Analog Devices

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Data Sheet
AD9544
Rev. 0 | Page 13 of 62
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TIMING
Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V
SCLK
Clock Rate, 1/tCLK
50
MHz
Pulse Width High, tHIGH
5
ns
Pulse Width Low, tLOW
9
ns
SDIO to SCLK Setup, tDS
2.2
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
9
ns
CSB to SCLK Setup, tS
1.5
ns
CSB to SCLK Hold, tC
0
ns
CSB Minimum Pulse Width High
1
tCLK
I2C Mode
Table 18.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SDA, SCL (AS INPUTS)
Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V
Input Logic 1 Voltage
70
% of VDDIOA
Input Logic 0 Voltage
0.3 ×
VDDIOA
V
Input Current
−10
+10
µA
For VIN = 10% to 90% of VDDIOA
Hysteresis of Schmitt Trigger Inputs
1.5
% of VDDIOA
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.2
V
IOUT = 3 mA
Output Fall Time from VIH Minimum
to VIL Maximum
20 + 0.1 × CB
250
ns
10 pF ≤ CB ≤ 400 pF
TIMING
SCL Clock Rate
400
kHz
Bus Free Time Between a Stop and
Start Condition, tBUF
1.3
µs
Repeated Start Condition Setup
Time, tSU; STA
0.6
µs
Repeated Hold Time Start
Condition, tHD; STA
0.6
µs
After this period, the first clock pulse is
generated
Stop Condition Setup Time, tSU; STO
0.6
µs
Low Period of the SCL Clock, tLOW
1.3
µs
High Period of the SCL Clock, tHIGH
0.6
µs
SCL/SDA Rise Time, tR
20 + 0.1 × CB
300
ns
SCL/SDA Fall Time, tF
20 + 0.1 × CB
300
ns
Data Setup Time, tSU; DAT
100
ns
Data Hold Time, tHD; DAT
100
ns
Capacitive Load for Each Bus Line, CB
400
pF



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