AD9544SLASHPCBZ datasheet(57/62 Pages) AD

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Data Sheet

AD9544

Rev. 0 | Page 57 of 62

autoclearing bit). The other is to use an external signal via

an appropriately programmed multifunction pin. The user can

change as many register bits as desired before executing an

input/output update. The input/output update operation transfers

the buffer register contents to their active register counterparts.

Read

If the instruction word indicates a read operation, the next

N × 8 SCLK cycles clock out the data starting from the address

specified in the instruction word, where N is the number of

data bytes to read. Read data appears on the appropriate data

pin (SDIO or SDO) on the falling edge of SCLK. The user must

latch the read data on the rising edge of SCLK. Note that the

internal SPI control logic does not skip over blank registers

during a readback operation.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

SPI Instruction Word (16 Bits)

The MSB of the 16-bit instruction word is R/W, which indicates

whether the ensuing operation is read or write. The next 15 bits

are the register address (A14 to A0), which indicates the starting

that SPI controller ignores A14, treating it as Logic 0, because

the AD9544 has no register addresses requiring more than a

14-bit address word.

SPI MSB-/LSB-First Transfers

The AD9544 instruction word and payload can be transferred

MSB first or LSB first. The default for the AD9544 is MSB first.

To invoke LSB first mode, write a Logic 1 to Register 0x00, Bit 6.

Immediately after invoking LSB first mode, subsequent serial

control port operations are LSB first.

Address Ascension

If the address ascension bit (Register 0x0000, Bit 5) is Logic 0,

serial control port register addressing decrements from the

specified starting address toward Address 0x0000. If the address

ascension bit (Register 0x0000, Bit 5) is Logic 1, serial control

port register addressing increments from the starting address

toward Address 0x3A3B. Reserved addresses are not skipped

during multibyte input/output operations; therefore, write the

default value to a reserved register and Logic 0s to unmapped

registers. Note that it is more efficient to issue a new write

command than to write the default value to more than two

consecutive reserved (or unmapped) registers.

Table 34. Streaming Mode (No Addresses Skipped)

Address Ascension

Stop Sequence

Increment

0x0000 … 0x3A3B

Decrement

0x3A3B … 0x0000

Table 35. Serial Control Port, 16-Bit Instruction Word

MSB

LSB

I15

I14

I13

I12

I11

I10

R/W

A14

A13

A12

A11

A10

CSB

SCLK DON'T CARE

SDIO

A12

A13

A14

R/W

A11 A10 A9

D2 D1

DON'T CARE

16-BIT INSTRUCTION HEADER

Figure 53. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data

CSB

SCLK

SDIO

SDO

16-BIT INSTRUCTION HEADER

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

DON'T

CARE

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 54. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data

DON'T CARE

A14

A13

A12

A11

A10

DON'T CARE

R/W

tDS

tDH

tHIGH

tLOW

tCLK

CSB

SCLK

SDIO

Figure 55. Timing Diagram for Serial Control Port Write—MSB First

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