AD9544SLASHPCBZ datasheet(14/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 14 of 62

LOGIC INPUT SPECIFICATIONS (RESETB, M0 TO M6)

Table 19.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RESETB

Valid for 3.3 V ≥ VDDIOA ≥ 1.8 V; internal 100 kΩ pull-up resistor

Input High Voltage (VIH)

VDDIOA − 0.4

Input Low Voltage (VIL)

0.4

Input Current High (IINH)

µA

Input Current Low (IINL)

±15

±125

µA

LOGIC INPUTS (M0 to M6)

Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies to the M5 pin and

the M6 pin; VDDIOB applies to the M0, M1, M2, M3, and M4 pins;

the M3 and M4 pins have internal 100 kΩ pull-down resistors

Frequency Range

MHz

Input High Voltage (VIH)

VDDIOx − 0.4

Input Low Voltage (VIL)

0.4

Input Current (IINH, IINL)

±15

±125

µA

LOGIC OUTPUT SPECIFICATIONS (M0 TO M6)

Table 20.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (M0 to M6)

Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies for the M5 and

M6 pins; VDDIOB applies for M0 to M4; normal (default) output

drive current setting for M0 through M6

Frequency Range

MHz

Output High Voltage (VOH)

VDDIOx − 0.6

Load current = 10 mA

VDDIOx – 0.2

Load current = 1 mA

Output Low Voltage (VOL)

0.6

Load current = 10 mA

0.2

Load current = 1 mA

JITTER GENERATION (RANDOM JITTER)

Table 21.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

System clock doubler enabled; high phase margin mode enabled;

there is not a significant jitter difference between driver modes

Channel 0—DPLL0, APLL0

Channel 1 powered down

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

223

Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 38.88 MHz, fVCO =

2488.32 MHz, fOUT = 155.52 MHz, BWDPLL = 50 Hz, phase buildout

operation

Configuration 2—245.76 MHz

220

Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 30.72 MHz, fVCO =

2457.6 MHz, fOUT = 245.76 MHz, BWDPLL = 50 Hz, internal zero delay

operation

Configuration 3—491.52 MHz

235

Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz

temperature compensated crystal oscillator (TCXO), BWCOMP =

50 Hz, fREF = 1 Hz, fVCO = 2949.12 MHz, fOUT = 491.52 MHz, BWDPLL =

50 mHz, phase buildout operation

Configuration 4—125 MHz

213

Device configuration: fSYSCLK = 52 MHz XTAL, fCOMP = 19.2 MHz TCXO,

BWCOMP = 50 Hz, fREF = 125 MHz, fVCO = 2500 MHz, fOUT = 125 MHz,

BWDPLL = 0.1 Hz, phase buildout operation

Configuration 5—312.5 MHz

217

Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 25 MHz, fVCO =

2500 MHz, fOUT = 312.5 MHz, BWDPLL = 50 Hz, phase buildout

operation

Configuration 6—174.7030837 MHz

230

Device configuration: fSYSCLK = 52 MHz XTAL, fREF = 155.52 MHz, fVCO =

2620.5463 MHz, fOUT = (155.52 × 255/227) MHz, BWDPLL = 50 Hz

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AD9544/PCBZ 数据表(PDF) 14 Page - Analog Devices

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