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AD9544/PCBZ 数据表(PDF) 21 Page - Analog Devices |
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AD9544/PCBZ 数据表(HTML) 21 Page - Analog Devices |
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21 / 62 page ![]() Data Sheet AD9544 Rev. 0 | Page 21 of 62 Pin No. Mnemonic Input/ Output Pin Type Description 14 OUT0BP Output HCSL, LVDS, CML, CMOS PLL0 Output 0B. 15 OUT0BN Output HCSL, LVDS, CML, CMOS PLL0 Complementary Output 0B. 16, 21, 44 DNC DNC No Connect Do Not Connect. Leave these pins floating. 17 OUT0CP Output HCSL, LVDS, CML, CMOS PLL0 Output 0C. 18 OUT0CN Output HCSL, LVDS, CML, CMOS PLL0 Complementary Output 0C. 22 OUT1BP Output HCSL, LVDS, CML, CMOS PLL1 Output 1B. 23 OUT1BN Output HCSL, LVDS, CML, CMOS PLL1 Complementary Output 1B. 25 OUT1AP Output HCSL, LVDS, CML, CMOS PLL1 Output 1A. 26 OUT1AN Input/ Output HCSL, LVDS, CML, CMOS PLL1 Complementary Output 1A. 29 LF1 Input/ output Loop filter for APLL1 Loop Filter Node for APLL1. Connect a 3.9 nF capacitor from this pin to Pin 30 (LDO1). 30 LDO1 Input LDO bypass APLL1 Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from this pin to ground. This pin is the ac ground reference for the integrated APLL1 loop filter. 32, 33, 35, 36, 37 M0, M1, M2, M3, M4 Input/ output CMOS Configurable Input/Output Pins. These are status and control pins. Changes to the VDDIOB supply voltage affect the VIH and VOH values for these pins. M3 and M4 have internal 100 kΩ pull-down resistors. M0, M1, and M2 do not have internal resistors. 34 VDDIOB Input Power Mx Pin Power Supply. This power supply powers the digital section that controls the M0 to M4 pins. Valid supply voltages are 1.8 V, 2.5 V, or 3.3 V. The VDDIOB pin can be connected to the VDD supply bus if 1.8 V operation is desired. 38 REFB Input 1.8 V single- ended or differential input Reference B Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with a single-ended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single- ended 1.8 V CMOS. 39 REFBB Input 1.8 V single- ended or differential input Reference BB Input or Complementary Reference B Input. If REFB is in differential mode, the REFB complementary signal is on this pin. No connection is necessary to this pin if REFB is a single-ended input and REFBB is not used. 42 XOA Input Differential input System Clock Input. XOA contains internal dc biasing and is ac-coupled with a 0.01 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. A single-ended CMOS input is also an option, but it can produce spurious spectral content when the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.1 μF capacitor from XOB to ground. 43 XOB Input Differential input Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and is ac-coupled with a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. 46 REFAA Input 1.8 V single- ended or differential input Reference AA input or Complementary REFA Input. If REFA is in differential mode, the REFA complementary signal is on this pin. No connection is necessary to this pin if REFA is a single-ended input and REFAA is not used. If dc-coupled, the input is single-ended 1.8 V CMOS. 47 REFA Input 1.8 V single- ended or differential input Reference A Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with a single-ended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single- ended 1.8 V CMOS. 48 RESETB Input 1.8 V CMOS logic Active Low Chip Reset. This pin has an internal 100 kΩ pull-up resistor. When asserted, the chip goes into reset. Changes to the VDDIOA supply voltage affect the VIH values for this pin. EP EPAD Output Exposed pad Exposed Pad. The exposed pad is the ground connection on the chip. The exposed pad must be soldered to the analog ground of the PCB to ensure proper functionality and for heat dissipation, noise, and mechanical strength benefits. |
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