AD9544SLASHPCBZ datasheet(32/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 32 of 62

DIGITAL PLL (DPLL)

OVERVIEW

Note that throughout this section, unless otherwise specified,

any referenced bits, registers, or bit fields reside in the DPLL

Channel 0 and DPLL Channel 1 sections (Address 0x1000 to

Address 0x102A, and Address 0x1400 to Address 0x142A) of

the register map.

The DPLL is an all-digital implementation of a phase-locked

loop (PLL). Figure 40 shows the fundamental building blocks of

an APLL and a DPLL. An APLL typically relies on a VCO as the

frequency element for generating an output signal, where the

output frequency depends on an applied dc voltage. A DPLL, on

the other hand, uses a numerically controlled oscillator (NCO),

which relies on a digital frequency tuning word (FTW) to

produce the output frequency. A VCO inherently produces a

timing signal because it is, by definition, an oscillator, whereas

the AD9544 NCO requires an external timing source, the system

clock. The fundamental difference between an APLL and a

DPLL is that the VCO in an APLL can tune to any frequency

within its operating bandwidth, whereas the NCO in a DPLL

can only tune to discrete frequencies (by virtue of the FTW).

PHASE

DETECTOR

DIVIDER

LOOP

FILTER

VCO

ANALOG

PHASE

ERROR

VOLTAGE

FIXED LOOP

BANDWIDTH

APLL

DIGITAL

PHASE

DETECTOR

DIVIDER

DIGITAL

LOOP

FILTER

NUMERIC

PHASE

ERROR

SYSTEM

CLOCK

PROGRAMMABLE

LOOP BANDWIDTH

DPLL

NCO

NUMERIC

COEFFICIENTS

NUMERIC

FREQUENCY

TUNING WORD

Figure 40. APLL vs. DPLL

The DPLLs in the AD9544 have a digital TDC-based phase

detector and a digital loop filter with programmable bandwidth.

The digital loop filter output yields a digital FTW (instead of a

dc voltage, as in the case of an analog PLL) that produces a

corresponding NCO output frequency.

DPLL PHASE/FREQUENCY LOCK DETECTORS

See the Lock Detectors section for details concerning the phase

and frequency detectors of the DPLL.

DPLL LOOP CONTROLLER

The DPLL has several operating modes (including freerun,

holdover, and active). To ensure seamless transition between

modes, the DPLL has a loop controller. The loop controller sets

the appropriate DPLL operating mode based on the prevailing

requirements of automatic reference switching or manual

control settings.

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another. The AD9544 handles a

reference switchover by briefly entering holdover mode, loading

the new DPLL parameters, and then immediately recovering.

Holdover

Typically, the holdover state is in effect when all of the input

references are invalid. However, the user can force the holdover

mode even when one or more references are valid by setting the

DPLLx force holdover bit (where x = 0 or 1) in the Operational

Control Channel 0 and Operational Control Channel 1 sections

of the register map to Logic 1. In holdover mode, the output

frequency remains fixed (to the extent of the stability of the

system clock). The accuracy of the AD9544 in holdover mode is

dependent on the device programming and availability of the

tuning word history.

Recovery from Holdover

When in holdover and an enabled translation profile becomes

available, the device exits holdover operation. The loop controller

restores the DPLL to closed-loop operation, locks to the selected

reference, and sequences the recovery of all the loop parameters

based on the profile settings for the active reference.

If the DPLLx force holdover bit (where x = 0 or 1) in the

Operational Control Channel 0 and Operational Control

Channel 1 sections of the register map is set to Logic 1, the

device does not automatically exit holdover when a valid

translation profile is available. However, automatic recovery can

occur after clearing the DPLL force holdover bit.

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