AD9544SLASHPCBZ datasheet(40/62 Pages) AD

40 / 62 page

AD9544

Data Sheet

Rev. 0 | Page 40 of 62

When configured as an Mx control pin, the logical level applied

to the Mx pin translates to the selected device function. It is also

possible to assign multiple Mx control pins to the same control

function with the multiple pins implementing a Boolean expres-

sion. The Boolean operation associated with an Mx control pin

depends on a 2-bit code per Table 29. The 2-bit codes reside in

constitute the Mx receiver/driver bit fields. Note that the Mx

receiver/driver bit fields perform a different function when the

Mx pin is a status pin (see the Status Functionality section).

Table 29. Mx Receiver/Driver Bit Field Codes for Mx Control

Pins

Code

Boolean

Description

AND

Logical AND the associated Mx control pin

with the other Mx control pins assigned to

the same control function.

NOT AND

Invert the logical state of the associated Mx

control pin and AND it with the other Mx

control pins assigned to the same control

function.

Logical OR the associated Mx control pin with

the other Mx control pins assigned to the

same control function.

NOT OR

Invert the logical state of the associated Mx

control pin and OR it with the other Mx control

pins assigned to the same control function.

The Boolean functionality of aggregated Mx control pins

follows a hierarchy whereby logical OR operations occur before

logical AND operations. The OR and NOT OR operations are

collectively grouped into a single result. A logical AND is then

performed using that result and the remaining AND and NOT

AND operations.

Consider a case where M0, M2, M3, and M6 are all assigned to

the input/output update control function; that is, Bits[D6:D0] in

addition, M0 is assigned for AND operation, M2 for NOT OR

operation, M3 for NOT AND operation, and M6 for OR operation

(that is, the 2-bit codes in Register 0x0100 and Register 0x0101

according to Table 29). With these settings, the input/output

update function behaves according the following Boolean equation:

Input/output update = (!M2 || M6) && M0 && !M3

where:

! is logical NOT. Therefore, an input/output update occurs when

M0 is Logic 1 and M3 is Logic 0, and either M2 is Logic 0 or M6

is Logic 1.

&& is logical AND.

|| is logical OR.

When an Mx control pin acts on a control function individually

(rather than as part of a group, per the previous example), the

Boolean functionality of the codes in Table 29 reduces to two

possibilities. Namely, Code 00 and Code 10 specify a Boolean

true (the Mx pin logic state applies to the corresponding control

function directly), whereas Code 01 and Code 11 specify a

Boolean false (the Mx pin logic state applies to the corresponding

control function with a logical inversion).

Regarding the source and destination proxy columns in Table 30,

the &&, || and ! symbols denote the Boolean AND, OR, and

NOT operations, respectively.

Table 30. Mx Pin Status and Control Codes

Bits[D6:D0]

(Hex)

Control Function

Destination Proxy

Status Function

Source Proxy (or Description)

0x00

No operation (NOOP)

Not applicable

Logic 0, static

Not applicable

0x01

IO_UPDATE

Logic 1, static

Not applicable

0x02

Device power down

Digital core clock

Not applicable

0x03

Clear watchdog timer

Watchdog timer timeout

Not applicable

0x04

Sync all

SYSCLK calibration in

progress

0x05

Unassigned

Not applicable

SYSCLK lock detect

0x06

Unassigned

Not applicable

SYSCLK stable

0x07

Unassigned

Not applicable

Channel 0 and Channel 1

PLLs locked

0x08

Unassigned

Not applicable

PLL0 locked

0x09

Unassigned

Not applicable

PLL1 locked

0x0A

Unassigned

Not applicable

EEPROM save in progress

0x0B

Unassigned

Not applicable

EEPROM load in progress

0x0C

Unassigned

Not applicable

EEPROM fault detected

0x0D

Unassigned

Not applicable

Temperature sensor limit

alarm

0x0E

Unassigned

Not applicable

Unassigned

Not applicable

0x0F

Unassigned

Not applicable

Unassigned

Not applicable

0x10

Clear all IRQ events

Any IRQ event

The logical OR of all triggered

IRQ events

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