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AD9544/PCBZ 数据表(PDF) 6 Page - Analog Devices

部件名 AD9544/PCBZ
功能描述  Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9544/PCBZ 数据表(HTML) 6 Page - Analog Devices

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AD9544
Data Sheet
Rev. 0 | Page 6 of 62
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Input Reference On/Off
Differential (Normal Mode)
20
mW
fREF = 19.44 MHz
Differential (DC-Coupled LVDS)
21
mW
fREF = 19.44 MHz
Single-Ended
13
mW
fREF = 19.44 MHz
Output Distribution Driver On/Off
At 156.25 MHz
15 mA Mode
30
mW
12 mA Mode
23
mW
7.5 mA Mode
15
mW
Auxiliary DPLL On/Off
1
mW
SYSTEM CLOCK INPUTS, XOA AND XOB
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM CLOCK MULTIPLIER
Output Frequency Range
2250
2415
MHz
The frequency range of the internal voltage controlled
oscillator (VCO) places limits on the choice of the system
clock input frequency
Phase Frequency Detector (PFD) Rate
20
300
MHz
SYSTEM CLOCK REFERENCE INPUT PATH
System clock input must be ac-coupled
Input Frequency Range
System Clock Input Doubler
Disabled
20
300
MHz
Support of oven controlled crystal oscillators (OCXOs) <
20 MHz is possible using the auxiliary DPLL for system clock
frequency compensation
Enabled
16
150
MHz
Self Biased Common-Mode Voltage
0.75
V
Internally generated
Input Voltage
For dc-coupled, single-ended operation
High
0.9
V
Low
0.5
V
Differential Input Voltage Sensitivity
250
mV p-p
Minimum voltage swing required (as measured with a
differential probe) across the XOA/XOB pins to ensure
switching between logic states; the instantaneous voltage on
either pin must not exceed 1.2 V; accommodate the single-
ended input by ac grounding the complementary input;
800 mV p-p recommended for optimal jitter performance
Slew Rate for Sinusoidal Input
50
V/µs
Minimum input slew rate for device operation; oscillators
with square wave outputs are recommended if not using a
crystal
System Clock Input Divider
(J Divider) Frequency
100
MHz
System Clock Input Doubler
Duty Cycle
Tolerable duty cycle variation on the system clock input
when using the frequency doubler
20 MHz to 150 MHz
43
50
57
%
16 MHz to 20 MHz
47
50
53
%
Input Resistance
5
kΩ
QUARTZ CRYSTAL RESONATOR PATH
Resonator Frequency Range
25
60
MHz
Fundamental mode, AT cut crystal
Crystal Motional Resistance
100
A maximum motional resistance of 50 Ω , and maximum
CLOAD of 8 pF is strongly recommended for crystals >52 MHz



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