AD9544SLASHPCBZ datasheet(47/62 Pages) AD

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Data Sheet

AD9544

Rev. 0 | Page 47 of 62

LOCK DETECTORS

DPLL LOCK DETECTORS

DPLL Phase Lock Detector

Each DPLL channel (DPLL0 and DPLL1) contains an all digital

phase lock detector. The user controls the threshold sensitivity

and hysteresis of the phase detector via the source profiles.

The phase lock detector provides the user with two status bits in

the status readback PLLx section of the register map. The DPLLx

phase lock bit latches to Logic 1 when the DPLL changes state

from not phase locked to phase locked. The DPLLx phase unlock

bit latches to Logic 1 when the DPLL changes state from phase

locked to not phase locked. The DPLLx phase lock bits are

located in Register 0x3100 and 0x3200, respectively. Because

these bits can change dynamically, it is strongly recommended

that the user set an IRQ for these bits. When using the IRQ

function, it is possible for the IRQ status to indicate Logic 1 for

an IRQ function that was just enabled if that condition is true at

the time the IRQ is enabled. Therefore, the user must clear the

IRQ just enabled via the IRQ map DPLL0 clear (Register 0x200B

to Register 0x200F) section and the IRQ map DPLL1 clear

(Register 0x2010 to Register 0x2014) section of the register map to

obtain visibility of subsequent state transitions of the phase lock

detector.

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 49). The total capacity of the tub

is 4096 units, with −2048 denoting empty, 0 denoting the 50%

point, and +2047 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark

at −1025 and a high water mark at +1024. To change the water

level, the phase lock detector adds water with a fill bucket or

removes water with a drain bucket. To specify the size of the fill

and drain buckets, use the unsigned 8-bit Profile x phase lock fill

rate and Profile x phase lock fill rate bit field (where x is a value

from 0 through 7, corresponding to a particular source profile).

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. When the water level

is below the low water mark (−1025), the lock detector indicates

an unlock condition. Conversely, when the water level is above

the high water mark (+1024), the lock detector indicates a lock

condition. When the water level is between the marks, the lock

detector holds its last condition. Figure 49 shows this concept

with an overlay of an example of the instantaneous water level

(vertical) vs. time (horizontal) and the resulting lock/unlock

states.

2047

–2048

1024

–1025

LOCK LEVEL

UNLOCK LEVEL

LOCKED

UNLOCKED

STATE

FILL

RATE

DRAIN

RATE

Figure 49. Lock Detector Diagram

During any given PFD phase error sample, the lock detector

either adds water with the fill bucket or removes water with the

drain bucket (one or the other, but not both). The decision of

whether to add or remove water depends on the threshold level

specified by the user in the 24-bit unsigned Profile x phase lock

threshold bit field. The bit field value is the desired threshold in

picoseconds. Thus, the phase lock threshold extends from 0 ps

to 16.7 µs and represents the phase error at the output of the

PFD. Though the programming range supports 0 ps as a lower

limit, in practice, the minimum value must be greater than 50 ps.

The phase lock detector compares the absolute value of each

phase error sample at the output of the PFD to the programmed

phase threshold value. If the absolute value of the phase error

sample is less than or equal to the programmed phase threshold

value, the detector control logic adds one fill bucket into the

tub. Otherwise, it removes one drain bucket from the tub. Note

that it is the magnitude, relative to the phase threshold value,

that determines whether to fill or drain the bucket, and not the

polarity of the phase error sample.

An exception to the fill/drain process occurs when the phase

slew limiter is active. When the phase slew limiter is actively in

the limiting process, the lock detector blocks fill events, allowing

only drain events to occur.

When more filling is taking place than draining, the water level

in the tub eventually rises above the high water mark (+1024),

which causes the lock detector to indicate lock. When more

draining is taking place than filling, the water level in the tub

eventually falls below the low water mark (−1024), which causes

the lock detector to indicate unlock. The ability to specify the

threshold level, fill rate, and drain rate enables the user to tailor

the operation of the lock detector to the statistics of the timing

jitter associated with the input reference signal. Note that, for

debug purposes, the user can make the fill or drain rate zero to

force the lock detector to indicate a lock or unlock state,

respectively.

Note that whenever the AD9544 enters freerun or holdover

mode, the DPLL phase lock detector indicates an unlocked state.

For more information on how to choose the appropriate phase

lock threshold, fill rate, and drain rate values for a given

application, refer to the AN-1061 Application Note.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that

of the phase lock detector, with two exceptions:

•

The fill or drain decision is based on the period deviation

between the reference of the DPLL and the feedback

signals, instead of the phase error at the output of the PFD.

•

The frequency lock detector is unaffected by the state of

the phase slew limiter.

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