AD9544SLASHPCBZ datasheet(33/62 Pages) AD

33 / 62 page

Data Sheet

AD9544

Rev. 0 | Page 33 of 62

APPLICATIONS INFORMATION

OPTICAL NETWORKING LINE CARD

In this application (shown in Figure 41), the AD9544 is used in

a variety of ways.

In a loop timed (WAN) mode, one of the AD9544 DPLLs locks

to the CDR and is used to remove jitter on the receiver path,

sending that clock to the central timing card, as well as the

framer. In some applications, the AD9544 can also perform a

variety of frequency translation tasks, such as multiplying or

dividing by an FEC ratio, and/or removing jitter from a gapped

clock. The other DPLL cleans jitter and provides clocking to the

transmitter path.

Other tasks include frequency translation and jitter cleaning of

the reference clock from the timing card, as well as seamlessly

managing the reference switching from Timing Card 1 to

Timing Card 2.

Given the continually evolving nature of optical line card

protocols and functions, the functions listed in this section are

by no means exhaustive.

FIBER

SYSTEM

CLOCK PLL

STATUS AND

CONTROL PINS

AD9544

LINE CARD

TEMPERATURE

SENSOR

SYSTEM CLOCK

COMPENSATION

REFERENCE

SWITCHING

CONTROL

REFERENCE

MONITORS

TDC

REFERENCE

INPUTS

NCO

DPLL

DPLL0

PLL

APLL0

VCO

NCO

DPLL

DPLL1

PLL

APLL1

VCO

PLL0

PLL1

DISTRIBUTION

OUTPUTS

DISTRIBUTION

OUTPUTS

÷2

÷Q

÷R

OUT0AP,

OUT0AN,

OUT0BP,

OUT0BN,

OUT0CP,

OUT0CN

OUT1AP,

OUT1AN,

OUT1BP,

OUT1BN

XOA,

XOB

INTERNAL ZERO DELAY

EEPROM

(OPTIONAL)

SYSTEM

CLOCK

DIGITAL

CROSS

POINT

MUX

SERIAL PORT (SPI/I2C)

AND EEPROM

CONTROLLER

M0 TO M6

REFA,

REFAA,

REFB,

REFBB

÷2

÷Q

FROM TIMING

CARD 1

FROM TIMING

CARD 2

FRAMER/FEC

SERIALIZER

FRAMER/FEC

DESERIALIZER CDR

LDD

LASER

DIODE

TIA

PHOTO

DIODE

POST

AMP

OPTICAL

MODULE

SERIAL PORT

Figure 41. Optical Line Card Example

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