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Z8F021ASH020SC 数据表(PDF) 120 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 120 Page - Zilog, Inc. |
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120 / 276 page ![]() PS022815-0206 UART Z8 Encore! XP® 4K Series Product Specification 101 TXD—Transmit Data UART transmitter data byte to be shifted out through the TXDx pin. UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data (UxRXD) register (Table 63). The read-only UART Receive Data register shares a Regis- ter File address with the Write-only UART Transmit Data register. RXD—Receive Data UART receiver data byte from the RXDx pin UART Status 0 Register The UART Status 0 (UxSTAT0) and Status 1(UxSTAT1) registers (Tables 64 and 65) iden- tify the current UART operating configuration and status. RDA—Receive Data Available This bit indicates that the UART Receive Data register has received data. Reading the UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. PE—Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data regis- ter clears this bit. Table 63. UART Receive Data Register (U0RXD) BITS 7 6 5 4 3 2 1 0 FIELD RXD RESET XX XX XXX X R/W R R R RRR RR ADDR F40H Table 64. UART Status 0 Register (U0STAT0) BITS 7 6 5 4 3 2 1 0 FIELD RDA PE OE FE BRKD TDRE TXE CTS RESET 00 00 0 1 1 X R/W RR RR R R R R ADDR F41H |
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