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Z8F021ASH020SC 数据表(PDF) 123 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 123 Page - Zilog, Inc. |
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123 / 276 page ![]() PS022815-0206 UART Z8 Encore! XP® 4K Series Product Specification 104 REN—Receive Enable This bit enables or disables the receiver. 0 = Receiver disabled. 1 = Receiver enabled. CTSE—CTS Enable 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. PEN—Parity Enable This bit enables or disables parity. Even or odd is determined by the PSEL bit. 0 = Parity is disabled. 1 = The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit. PSEL—Parity Select 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. SBRK—Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending data before setting this bit. 0 = No break is sent. 1 = Forces a break condition by setting the output of the transmitter to zero. STOP—Stop Bit Select 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. LBEN—Loop Back Enable 0 = Normal operation. 1 = All transmitted data is looped back to the receiver. MPMD[1:0]—MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an Table 67. UART Control 1 Register (U0CTL1) BITS 7 6 5 4 3 2 1 0 FIELD MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN RESET 00 00 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W ADDR F43H |
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