Z8F021ASH020SC datasheet(122/276 Pages) ZILOG

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PS022815-0206

UART

Z8 Encore! XP® 4K Series

Product Specification

103

UART Status 1 Register

This register contains multiprocessor control and status bits.

Reserved—Must be 0.

NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive

Data register resets this bit to 0.

0 = The current byte is not the first data byte of a new frame.

1 = The current byte is the first data byte of a new frame.

MPRX—Multiprocessor Receive

Returns the value of the most recent multiprocessor bit received. Reading from the UART

Receive Data register resets this bit to 0.

UART Control 0 and Control 1 Registers

The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers (Tables 66 and 67)

configure the properties of the UART’s transmit and receive operations. The UART Con-

trol registers must not be written while the UART is enabled.

TEN—Transmit Enable

This bit enables or disables the transmitter. The enable is also controlled by the CTS signal

and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is

enabled.

0 = Transmitter disabled.

1 = Transmitter enabled.

Table 65. UART Status 1 Register (U0STAT1)

BITS

FIELD

Reserved

NEWFRM

MPRX

RESET

R/W

ADDR

F44H

Table 66. UART Control 0 Register (U0CTL0)

BITS

FIELD

TEN

REN

CTSE

PEN

PSEL

SBRK

STOP

LBEN

RESET

000

R/W

R/WR/W

ADDR

F42H

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