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DSP56303 数据表(PDF) 239 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 239 Page - Freescale Semiconductor, Inc |
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239 / 292 page  Phase Locked Loop (PLL) equates DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor A-17 M_DAM0 EQU4 ; DMA Address Mode 0 M_DAM1 EQU5 ; DMA Address Mode 1 M_DAM2 EQU6 ; DMA Address Mode 2 M_DAM3 EQU7 ; DMA Address Mode 3 M_DAM4 EQU8 ; DMA Address Mode 4 M_DAM5 EQU9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode M_DRS EQU$F800 ; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU16 ; DMA Continuous Mode M_DPR EQU$60000 ; DMA Channel Priority M_DPR0 EQU17 ; DMA Channel Priority Level (low) M_DPR1 EQU18 ; DMA Channel Priority Level (high) M_DTM EQU$380000 ; DMA Transfer Mode Mask ;(DTM2-DTM0) M_DTM0 EQU19 ; DMA Transfer Mode 0 M_DTM1 EQU20 ; DMA Transfer Mode 1 M_DTM2 EQU21 ; DMA Transfer Mode 2 M_DIE EQU22 ; DMA Interrupt Enable bit M_DE EQU23 ; DMA Channel Enable bit ; DMA Status Register M_DTD EQU $3F ;Channel Transfer Done Status MASK M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0 M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1 M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2 M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5 M_DACT EQU 8 ; DMA Active State M_DCH EQU $E00 ; DMA Active Channel Mask : (DCH0DCH2) M_DCH0 EQU 9 ; DMA Active Channel 0 M_DCH1 EQU 10 ; DMA Active Channel 1 M_DCH2 EQU 11 ; DMA Active Channel 2 ;--------------------------------------------------------------- A.9 Phase Locked Loop (PLL) equates ;--------------------------------------------------------------- ; Register Addresses Of PLL M_PCTL EQU $FFFFFD ; PLL Control Register ; PLL Control Register M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11) M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 ; XTAL Range select bit |
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