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数据搜索系统，热门电子元器件搜索 |
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DSP56303 数据表(PDF) 240 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 240 Page - Freescale Semiconductor, Inc |
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240 / 292 page  DSP56303 User’s Manual, Rev. 2 A-18 Freescale Semiconductor Bootstrap Program M_XTLD EQU 16 ; XTAL Disable Bit M_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable Bit M_PCOD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3) ;--------------------------------------------------------------- A.10 Bus Interface Unit (BIU) Equates ;--------------------------------------------------------------- ; Register Addresses Of BIU M_BCR EQU $FFFFFB ; Bus Control Register M_DCR EQU $FFFFFA ; DRAM Control Register M_AAR0 EQU $FFFFF9 ; Address Attribute Register 0 M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2 M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3 M_IDR EQU $FFFFF5 ; ;ID Register ; Bus Control Register M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4) M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 ; Bus State M_BLH EQU 22 ; Bus Lock Hold M_BRH EQU 23 ; Bus Request Hold ; DRAM Control Register M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7) M_BRP EQU 23 ; Refresh prescaler ; Address Attribute Registers M_BAT EQU $3 ; External Access Type and Pin Definition Bits ;Mask BAT(1:0) M_BAAP EQU 2 ; Address Attribute Pin Polarity M_BPEN EQU 3 ; Program Space Enable |
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