| 数据搜索系统,热门电子元器件搜索 |
|
DSP56303 数据表(PDF) 245 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
DSP56303 数据表(HTML) 245 Page - Freescale Semiconductor, Inc |
|
245 / 292 page ![]() DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor B-1 Programming Reference B This reference for programmers includes a table showing the addresses of all DSP memory-mapped peripherals, an exception priority table, and programming sheets for the major programmable DSP registers. The programming sheets are grouped in the following order: central processor, Phase Lock Loop (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, and GPIO. Each sheet provides room to write in the value of each bit and the hexadecimal value for each register. You can photocopy these sheets and reuse them for each application development project. For details on the instruction set of the DSP56300 family of DSPs, see the DSP56300 Family Manual. Table B-2, Internal I/O Memory Map (X Data Memory), on page B-2 lists the memory addresses of all internal peripherals. Table B-3, Interrupt Sources, on page B-6 lists the interrupt starting addresses and sources. Table B-4, Interrupt Source Priorities Within an IPL, on page B-8 lists the priorities of specific interrupts within interrupt priority levels. The programming sheets appear in this manual as figures (listed in Table B-1); they show the major programmable registers on the DSP56303. Table B-1. Guide to Programming Sheets Module Programming Sheet Page Central Processor Figure B-1, "Status Register (SR)" page B-10 Figure B-2, "Operating Mode Register (OMR)" page B-11 IPR Figure B-3, "Interrupt Priority Register-Peripherals (IPRP)" page B-12 Figure B-3, "Interrupt Priority Register-Peripherals (IPRP)" page B-12 PLL Figure B-4, "Phase-Locked Loop Control Register (PCTL)" page B-13 BIU Figure B-5, "Bus Control Register (BCR)" page B-14 Figure B-6, "DRAM Control Register (DCR)" page B-15 Figure B-7, "Address Attribute Registers (AAR[3–0])" page B-16 DMA Figure B-8, "DMA Control Registers 5–0 (DCR[5–0])" page B-17 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |